公开(公告)号：US5923069A

公开(公告)日：1999-07-13

申请号：US891098

申请日：1997-07-10

申请人： Jong-Hoon Park ,  Jae-Woon Kim

发明人： Jong-Hoon Park ,  Jae-Woon Kim

IPC分类号： G01R19/00 ,  G11C11/417 ,  H03K5/08 ,  H03K19/0175 ,  H01L29/76

CPC分类号： H03K5/08

摘要： An improved voltage level detecting circuit that provides stable voltage detection. The voltage level detecting circuit senses a level of a voltage to be detected only when two clock signals are at a low level after ORing the signals. After detecting the voltage level, the circuit reduces power consumption by preventing a current path between the voltage and ground. Consistent operation of the voltage level detecting circuit is achieved despite fluctuation of the voltage level to be detected caused by noise through detecting the level of the voltage only when a specific clock signal is enabled.

摘要翻译： 提供稳定电压检测的改进的电压电平检测电路。 电压电平检测电路仅在两个时钟信号在对信号进行或运算之后处于低电平时才感测到要检测的电压电平。 在检测到电压电平后，电路通过防止电压和地之间的电流路径来降低功耗。 尽管通过仅在特定的时钟信号被使能时通过检测电压的电平来实现由噪声引起的待检测的电压电平的波动来实现电压电平检测电路的一致的操作。

公开(公告)号：US06314038B1

公开(公告)日：2001-11-06

申请号：US09754119

申请日：2001-01-05

申请人： Jae-Woon Kim ,  Jong-Hoon Park

发明人： Jae-Woon Kim ,  Jong-Hoon Park

IPC分类号： G11C700

CPC分类号： G11C7/106 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18

摘要： A semiconductor memory includes a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells outputs a first data signal through an I/O line; an I/O line driving circuit for generating a second data signal by amplifying the first data signal, wherein the I/O line driving circuit is connected to the I/O lines; a data bus driving circuit connected to the I/O line driving circuit to generate a third data signal by amplifying the second data signal; a data bus precharge circuit; and a data bus connecting the data bus driving circuit to the data bus precharge circuit, wherein the data bus precharge circuit precharges the data bus to a predetermined voltage level before the third data signal is generated and transfers a voltage of the data bus to high or low level in accordance with a logic value of the third data signal when the third data signal is generated.

摘要翻译： 半导体存储器包括存储单元阵列，其包括多个存储单元，其中多个存储单元中的每一个通过I / O线输出第一数据信号; I / O线驱动电路，用于通过放大第一数据信号来产生第二数据信号，其中I / O线驱动电路连接到I / O线; 连接到I / O线驱动电路的数据总线驱动电路，通过放大第二数据信号产生第三数据信号; 数据总线预充电电路; 以及将数据总线驱动电路连接到数据总线预充电电路的数据总线，其中，数据总线预充电电路在产生第三数据信号之前将数据总线预充电到预定的电压电平，并将数据总线的电压传送到高或 当产生第三数据信号时，根据第三数据信号的逻辑值的低电平。

公开(公告)号：US5654664A

公开(公告)日：1997-08-05

申请号：US623083

申请日：1996-03-28

申请人： Jong-Hoon Park ,  Jae-Woon Kim

发明人： Jong-Hoon Park ,  Jae-Woon Kim

IPC分类号： G11C11/417 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948 ,  H01J19/82

CPC分类号： H03K19/0027

摘要： An input buffer circuit of a semiconductor memory capable of controlling a logic threshold voltage of the circuit according to a change in an external supply voltage, which includes an external supply voltage detecting unit for dividing the external supply voltage into a plurality of regions by comparing a plurality of voltages, which have been divided by different ratios of the entire external supply voltage, with a standard voltage; and a converting unit including a pull-up circuit and a pull-down circuit, for converting input signals of TTL level into signals of CMOS level, according to the regions of the external supply voltage obtained by the external supply voltage detecting unit. The input buffer has an advantage in that margins for a logical high input range and logical low input range are improved when converting voltages of TTL level into voltages of CMOS level, by controlling the logic threshold voltage so as to lower the logic threshold voltage when the external supply voltage level is high and raise the logic threshold voltage when the external supply voltage level is low.

摘要翻译： 一种半导体存储器的输入缓冲电路，其能够根据外部电源电压的变化来控制电路的逻辑阈值电压，该外部电源电压包括外部电源电压检测单元，用于将外部电源电压分为多个区域， 已经将整个外部电源电压的不同比例除以多个电压与标准电压; 以及包括上拉电路和下拉电路的转换单元，用于根据由外部电源电压检测单元获得的外部电源电压的区域将TTL电平的输入信号转换成CMOS电平的信号。 输入缓冲器的优点在于，当通过控制逻辑阈值电压将TTL电平的电压转换成CMOS电平的电压来改善逻辑高输入范围和逻辑低输入范围的裕度，从而当逻辑门限电压 外部电源电压高，外部电源电压低时提高逻辑门限电压。

公开(公告)号：US06259649B1

公开(公告)日：2001-07-10

申请号：US09617278

申请日：2000-07-17

申请人： Jae-Woon Kim

发明人： Jae-Woon Kim

IPC分类号： G11C800

CPC分类号： G11C5/066

摘要： The present invention relates to a semiconductor memory circuit capable of reducing the number of routes to decrease the area of a chip. In a construction of a synchronous semiconductor memory circuit with a LOC architecture in accordance with the present invention including a peripheral circuit block in which an address pad and an input/output pad are arranged at the left and right sides of a chip, respectively, an address counter is placed at the center of the address pad, a first address decoder is placed at the address pad, a second address decoder is placed at the input/output pad, a first address counter buffer for driving the first address decoder upon receipt of the output of the address counter is placed adjacent to the address counter between the address counter and the first address decoder, and a second address counter buffer for driving the second address decoder upon receipt of the output of the address counter is placed at the center of the chip.

摘要翻译： 本发明涉及一种半导体存储器电路，其能够减少路径的数量以减小芯片的面积。 在根据本发明的具有LOC架构的同步半导体存储器电路的结构中，包括分别在芯片的左侧和右侧布置地址焊盘和输入/输出焊盘的外围电路块， 地址计数器被放置在地址块的中心，第一地址解码器被放置在地址焊盘处，第二地址解码器被放置在输入/输出焊盘处，第一地址计数器缓冲器，用于在接收到第一地址解码器时驱动第一地址解码器 地址计数器的输出与地址计数器和第一地址解码器之间的地址计数器相邻放置，并且用于在接收到地址计数器的输出时驱动第二地址解码器的第二地址计数器缓冲器被置于 芯片。

公开(公告)号：US06442716B1

公开(公告)日：2002-08-27

申请号：US09482678

申请日：2000-01-14

申请人： Jae-Woon Kim

发明人： Jae-Woon Kim

IPC分类号： G11C2900

CPC分类号： G11C7/1051

摘要： A data output buffer is disclosed that includes an input section receiving a data signal and an output enable signal to output a pull-up signal and a pull-down signal, a drive control section and a plurality of output driving sections. The drive control section activates less than all of the plurality of drive control signals in response to the data signal in a second mode and activates all the drive control signals in normal operations or a first mode. The plurality of output driving sections each receive the pull-up signal, the pull-down signal and one of the drive control signals to perform a pull-up operation or pull-down operation in accordance with the logic value of the data signal when activated.

摘要翻译： 公开了一种数据输出缓冲器，其包括接收数据信号的输入部分和用于输出上拉信号和下拉信号的输出使能信号，驱动控制部分和多个输出驱动部分。 驱动控制部分响应于第二模式中的数据信号激活少于所有多个驱动控制信号，并且在正常操作或第一模式下激活所有驱动控制信号。 多个输出驱动部各自接收上拉信号，下拉信号和驱动控制信号之一，以在激活时根据数据信号的逻辑值执行上拉操作或下拉操作 。