公开(公告)号：US06721209B2

公开(公告)日：2004-04-13

申请号：US10144783

申请日：2002-05-15

申请人： Jae Woon Kim

发明人： Jae Woon Kim

IPC分类号： G11C700

CPC分类号： G11C7/1012 ,  G11C7/1048 ,  G11C7/1051

摘要： A semiconductor memory device suitable for rapidly transferring output data from sense amplifiers to an output-buffer is disclosed. The semiconductor memory device includes a plurality of sense amplifiers respectively connected to a plurality of cell blocks. A first common output-line is connected to a first set of sense amplifiers associated with a first set of cell blocks. A second common output-line is connected to a second set of sense amplifiers associated with a second set of cell blocks. A loading selection circuit selects one of the first and second common output-lines so as to transfer output data from a selected sense amplifier, via the selected one of the first and second common output-lines, to another device, such as an output-buffer.

摘要翻译： 公开了一种适用于将输出数据从读出放大器快速传送到输出缓冲器的半导体存储器件。 半导体存储器件包括分别连接到多个单元块的多个读出放大器。 第一公共输出线连接到与第一组单元块相关联的第一组读出放大器。 第二公共输出线连接到与第二组单元块相关联的第二组读出放大器。 加载选择电路选择第一和第二公共输出行之一，以便经由所选择的第一和第二公共输出行之一将来自所选择的读出放大器的输出数据传送到诸如输出 - 缓冲。

公开(公告)号：US5682113A

公开(公告)日：1997-10-28

申请号：US534973

申请日：1995-09-27

申请人： Jong Hoon Park ,  Jae Woon Kim

发明人： Jong Hoon Park ,  Jae Woon Kim

IPC分类号： H03K5/04 ,  H03K3/017

CPC分类号： H03K5/04

摘要： A pulse extending circuit includes a pulse extension inverting device for extending an input pulse signal by a predetermined width; and a delay device for extending the signal output from the pulse extension inverting device; thereby increasing a delay effect.

摘要翻译： 脉冲延迟电路包括用于将输入脉冲信号延伸预定宽度的脉冲延伸反转装置; 以及延迟装置，用于延长从脉冲延伸反转装置输出的信号; 从而增加延迟效应。

公开(公告)号：US06531709B1

公开(公告)日：2003-03-11

申请号：US09715058

申请日：2000-11-20

申请人： Jae Woon Kim ,  Jong Hoon Park

发明人： Jae Woon Kim ,  Jong Hoon Park

IPC分类号： H01L2358

CPC分类号： H01L24/05 ,  H01L21/78 ,  H01L22/32 ,  H01L23/528 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/05599 ,  H01L2924/01004 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/00014

摘要： The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor wafer and a fabrication method of semiconductor chips. According to the present invention, a semiconductor wafer containing a plurality of semiconductor chip portions has a plurality of chip scribe lanes formed between the semiconductor chip portions. A plurality of chip bonding pads are formed on the semiconductor chip portions of the wafer, and a plurality of wafer probing pads are formed on the chip scribe lanes. The wafer probing pads are electrically connected to internal circuits of the semiconductor chip portions and/or to corresponding ones of the chip bonding pads.

摘要翻译： 半导体器件技术领域本发明涉及半导体器件，更具体地，涉及半导体晶片的结构和半导体芯片的制造方法。 根据本发明，包含多个半导体芯片部分的半导体晶片在半导体芯片部分之间形成有多个芯片划线。 在晶片的半导体芯片部分上形成多个芯片接合焊盘，并且在芯片划线上形成多个晶片探测焊盘。 晶片探测焊盘电连接到半导体芯片部分的内部电路和/或与芯片焊盘的相应芯片电连接。

公开(公告)号：US06259649B1

公开(公告)日：2001-07-10

申请号：US09617278

申请日：2000-07-17

申请人： Jae-Woon Kim

发明人： Jae-Woon Kim

IPC分类号： G11C800

CPC分类号： G11C5/066

摘要： The present invention relates to a semiconductor memory circuit capable of reducing the number of routes to decrease the area of a chip. In a construction of a synchronous semiconductor memory circuit with a LOC architecture in accordance with the present invention including a peripheral circuit block in which an address pad and an input/output pad are arranged at the left and right sides of a chip, respectively, an address counter is placed at the center of the address pad, a first address decoder is placed at the address pad, a second address decoder is placed at the input/output pad, a first address counter buffer for driving the first address decoder upon receipt of the output of the address counter is placed adjacent to the address counter between the address counter and the first address decoder, and a second address counter buffer for driving the second address decoder upon receipt of the output of the address counter is placed at the center of the chip.

摘要翻译： 本发明涉及一种半导体存储器电路，其能够减少路径的数量以减小芯片的面积。 在根据本发明的具有LOC架构的同步半导体存储器电路的结构中，包括分别在芯片的左侧和右侧布置地址焊盘和输入/输出焊盘的外围电路块， 地址计数器被放置在地址块的中心，第一地址解码器被放置在地址焊盘处，第二地址解码器被放置在输入/输出焊盘处，第一地址计数器缓冲器，用于在接收到第一地址解码器时驱动第一地址解码器 地址计数器的输出与地址计数器和第一地址解码器之间的地址计数器相邻放置，并且用于在接收到地址计数器的输出时驱动第二地址解码器的第二地址计数器缓冲器被置于 芯片。

公开(公告)号：US6159826A

公开(公告)日：2000-12-12

申请号：US154579

申请日：1998-09-17

申请人： Jae Woon Kim ,  Jong Hoon Park

发明人： Jae Woon Kim ,  Jong Hoon Park

IPC分类号： H01L21/66 ,  H01L21/60 ,  H01L21/78 ,  H01L23/485 ,  H01L23/528 ,  H01L23/58 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L21/78 ,  H01L22/32 ,  H01L23/528 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/05599 ,  H01L2924/01004 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/00014

摘要： The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor wafer and a fabrication method of semiconductor chips. According to the present invention, a semiconductor wafer containing a plurality of semiconductor chip portions has a plurality of chip scribe lanes formed between the semiconductor chip portions. A plurality of chip bonding pads are formed on the semiconductor chip portions of the wafer, and a plurality of wafer probing pads are formed on the chip scribe lanes. The wafer probing pads are electrically connected to internal circuits of the semiconductor chip portions and/or to corresponding ones of the chip bonding pads.

公开(公告)号：US20130201773A1

公开(公告)日：2013-08-08

申请号：US13724536

申请日：2012-12-21

申请人： Jae-woon KIM

发明人： Jae-woon KIM

IPC分类号： G11C7/22

CPC分类号： G11C7/22 ,  G11C7/14 ,  G11C17/18 ,  G11C29/027

摘要： A nonvolatile memory device includes an operation control unit, a reference voltage generating unit, and a sensing unit. The operation control unit is configured to select a unit cell from unit cells to perform reading and writing operations. The reference voltage generating unit is configured to voltage-divide a read voltage using series-connected resistors and generate a reference voltage based on the voltage-divided read voltage. The sensing unit is configured to compare a size of a voltage through an e-fuse of the selected unit cell based on the read voltage with the reference voltage, and sense data of the e-fuse of the selected unit cell. The nonvolatile memory device also includes a read current supply unit configured to output the read voltage to the unit cells during a reading operation of the nonvolatile memory device.

摘要翻译： 非易失性存储器件包括操作控制单元，参考电压产生单元和感测单元。 操作控制单元被配置为从单元单元中选择单位单元以执行读取和写入操作。 参考电压产生单元被配置为使用串联电阻器对读取电压进行分压，并且基于分压的读取电压产生参考电压。 感测单元被配置为基于读取的电压与参考电压以及所选择的单元的电子熔丝的感测数据来比较通过所选择的单位单元的电子熔丝的电压的大小。 非易失性存储器件还包括读出电流供给单元，被配置为在非易失性存储器件的读取操作期间将读取的电压输出到单位单元。

公开(公告)号：US06442716B1

公开(公告)日：2002-08-27

申请号：US09482678

申请日：2000-01-14

申请人： Jae-Woon Kim

发明人： Jae-Woon Kim

IPC分类号： G11C2900

CPC分类号： G11C7/1051

摘要： A data output buffer is disclosed that includes an input section receiving a data signal and an output enable signal to output a pull-up signal and a pull-down signal, a drive control section and a plurality of output driving sections. The drive control section activates less than all of the plurality of drive control signals in response to the data signal in a second mode and activates all the drive control signals in normal operations or a first mode. The plurality of output driving sections each receive the pull-up signal, the pull-down signal and one of the drive control signals to perform a pull-up operation or pull-down operation in accordance with the logic value of the data signal when activated.

摘要翻译： 公开了一种数据输出缓冲器，其包括接收数据信号的输入部分和用于输出上拉信号和下拉信号的输出使能信号，驱动控制部分和多个输出驱动部分。 驱动控制部分响应于第二模式中的数据信号激活少于所有多个驱动控制信号，并且在正常操作或第一模式下激活所有驱动控制信号。 多个输出驱动部各自接收上拉信号，下拉信号和驱动控制信号之一，以在激活时根据数据信号的逻辑值执行上拉操作或下拉操作 。

公开(公告)号：US06314038B1

公开(公告)日：2001-11-06

申请号：US09754119

申请日：2001-01-05

申请人： Jae-Woon Kim ,  Jong-Hoon Park

发明人： Jae-Woon Kim ,  Jong-Hoon Park

IPC分类号： G11C700

CPC分类号： G11C7/106 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18

摘要： A semiconductor memory includes a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells outputs a first data signal through an I/O line; an I/O line driving circuit for generating a second data signal by amplifying the first data signal, wherein the I/O line driving circuit is connected to the I/O lines; a data bus driving circuit connected to the I/O line driving circuit to generate a third data signal by amplifying the second data signal; a data bus precharge circuit; and a data bus connecting the data bus driving circuit to the data bus precharge circuit, wherein the data bus precharge circuit precharges the data bus to a predetermined voltage level before the third data signal is generated and transfers a voltage of the data bus to high or low level in accordance with a logic value of the third data signal when the third data signal is generated.

摘要翻译： 半导体存储器包括存储单元阵列，其包括多个存储单元，其中多个存储单元中的每一个通过I / O线输出第一数据信号; I / O线驱动电路，用于通过放大第一数据信号来产生第二数据信号，其中I / O线驱动电路连接到I / O线; 连接到I / O线驱动电路的数据总线驱动电路，通过放大第二数据信号产生第三数据信号; 数据总线预充电电路; 以及将数据总线驱动电路连接到数据总线预充电电路的数据总线，其中，数据总线预充电电路在产生第三数据信号之前将数据总线预充电到预定的电压电平，并将数据总线的电压传送到高或 当产生第三数据信号时，根据第三数据信号的逻辑值的低电平。

公开(公告)号：US5654664A

公开(公告)日：1997-08-05

申请号：US623083

申请日：1996-03-28

申请人： Jong-Hoon Park ,  Jae-Woon Kim

发明人： Jong-Hoon Park ,  Jae-Woon Kim

IPC分类号： G11C11/417 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948 ,  H01J19/82

CPC分类号： H03K19/0027

摘要： An input buffer circuit of a semiconductor memory capable of controlling a logic threshold voltage of the circuit according to a change in an external supply voltage, which includes an external supply voltage detecting unit for dividing the external supply voltage into a plurality of regions by comparing a plurality of voltages, which have been divided by different ratios of the entire external supply voltage, with a standard voltage; and a converting unit including a pull-up circuit and a pull-down circuit, for converting input signals of TTL level into signals of CMOS level, according to the regions of the external supply voltage obtained by the external supply voltage detecting unit. The input buffer has an advantage in that margins for a logical high input range and logical low input range are improved when converting voltages of TTL level into voltages of CMOS level, by controlling the logic threshold voltage so as to lower the logic threshold voltage when the external supply voltage level is high and raise the logic threshold voltage when the external supply voltage level is low.

摘要翻译： 一种半导体存储器的输入缓冲电路，其能够根据外部电源电压的变化来控制电路的逻辑阈值电压，该外部电源电压包括外部电源电压检测单元，用于将外部电源电压分为多个区域， 已经将整个外部电源电压的不同比例除以多个电压与标准电压; 以及包括上拉电路和下拉电路的转换单元，用于根据由外部电源电压检测单元获得的外部电源电压的区域将TTL电平的输入信号转换成CMOS电平的信号。 输入缓冲器的优点在于，当通过控制逻辑阈值电压将TTL电平的电压转换成CMOS电平的电压来改善逻辑高输入范围和逻辑低输入范围的裕度，从而当逻辑门限电压 外部电源电压高，外部电源电压低时提高逻辑门限电压。

公开(公告)号：US20110081522A1

公开(公告)日：2011-04-07

申请号：US12672070

申请日：2008-08-01

申请人： Jae Woon Kim

发明人： Jae Woon Kim

IPC分类号： B41M5/382 ,  B05D1/36 ,  B41M5/26

CPC分类号： B41M3/12 ,  B41M2205/10 ,  D06P5/003 ,  Y10T428/24504

摘要： A three-dimensional foaming type transfer paper with an enhanced durability and a method for manufacturing the same is disclosed. The transfer paper includes a releasing agent layer having a releasing sheet and formed on the releasing sheet using transparent silicon; a fluorine coating layer formed on the releasing agent layer; a silicon rubber layer formed only on a portion of the fluorine coating layer on which printing is to be performed, through a silk screen process; a first fluoride polyester layer formed on the silicon rubber layer; a printed layer formed on the first fluoride polyester layer using ink; a second fluoride polyester layer formed on the printed layer; a first foaming layer formed partially on the second fluoride polyester layer; a second foaming layer formed on the first foaming layer; and a thermal adhesive resin layer formed on the second foaming layer.

摘要翻译： 公开了一种耐久性提高的三维发泡型转印纸及其制造方法。 转印纸包括具有剥离片的脱模剂层，并使用透明硅形成在剥离片上; 形成在脱模剂层上的氟涂层; 通过丝网印刷方法仅在要进行印刷的氟涂层的一部分上形成硅橡胶层; 形成在硅橡胶层上的第一氟化物聚酯层; 使用油墨在所述第一氟化物聚酯层上形成的印刷层; 形成在印刷层上的第二氟化聚酯层; 第一发泡层部分地形成在第二氟化物聚酯层上; 形成在第一发泡层上的第二发泡层; 和形成在第二发泡层上的热粘合树脂层。