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公开(公告)号：US07786763B1
公开(公告)日：2010-08-31
申请号：US12346764
申请日：2008-12-30
Applicant: Jagdeep Bal , Tao Jing
Inventor： Jagdeep Bal , Tao Jing
IPC: H03D13/00
CPC classification number: H03D13/00
Abstract: A clock circuit includes a phase-lock loop for generating an output clock signal based on a data signal and a harmonic frequency detector for detecting whether the frequency of the output clock signal is a harmonic frequency of a frequency of a reference clock signal. The harmonic frequency detector includes a counter for generating a first divided clock signal by dividing the frequency of the output clock signal by a first divisor. Additionally, the harmonic frequency detector includes a counter for generating a second divided clock signal by dividing the frequency of the reference clock signal by a second divisor. The harmonic frequency detector also includes a frequency comparator for generating an output indicating whether the frequency of the output clock signal is a harmonic frequency of the frequency of the reference clock signal based on the first divided clock signal and the second divided clock signal.
Abstract translation: 时钟电路包括用于基于数据信号产生输出时钟信号的相位锁定回路和用于检测输出时钟信号的频率是否是参考时钟信号的频率的谐波频率的谐波频率检测器。 谐波频率检测器包括用于通过将输出时钟信号的频率除以第一除数来产生第一分频时钟信号的计数器。 此外，谐波频率检测器包括用于通过将参考时钟信号的频率除以第二除数来产生第二分频时钟信号的计数器。 谐波频率检测器还包括频率比较器，用于基于第一分频时钟信号和第二分频时钟信号产生指示输出时钟信号的频率是基准时钟信号的频率的谐波频率的输出。
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公开(公告)号：US08164367B1
公开(公告)日：2012-04-24
申请号：US12354453
申请日：2009-01-15
Applicant: Jagdeep Bal , Arvind Sridhar
Inventor： Jagdeep Bal , Arvind Sridhar
IPC: H03L7/06
CPC classification number: H03L7/16 , H03L7/1976 , H03L7/23
Abstract: A clock signal generator includes a phase-lock loop for generating an imaging clock signal having a frequency based on a reference clock signal. The imaging clock signal generator also includes a modulation circuit for determining a number of pixels in a horizontal line of an image to be generated based on the imaging clock signal. The modulation circuit generates a modulation signal based on the determined number of pixels and the clock signal generator spreads the frequency of the imaging clock signal across a frequency range based on the modulation signal. In this way, the clock signal generator reduces electromagnetic interference in the imaging clock signal. In further embodiments, the clock signal generator generates an adjustment signal for adjusting the frequency range based on the frequency of the reference clock signal and the frequency of the imaging clock signal.
Abstract translation: 时钟信号发生器包括用于产生具有基于参考时钟信号的频率的成像时钟信号的锁相环。 成像时钟信号发生器还包括调制电路，用于基于成像时钟信号来确定要生成的图像的水平线中的像素数。 调制电路基于所确定的像素数生成调制信号，并且时钟信号发生器基于调制信号在频率范围内扩展成像时钟信号的频率。 以这种方式，时钟信号发生器降低成像时钟信号中的电磁干扰。 在另外的实施例中，时钟信号发生器基于参考时钟信号的频率和成像时钟信号的频率产生用于调整频率范围的调整信号。
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公开(公告)号：US5764112A
公开(公告)日：1998-06-09
申请号：US703670
申请日：1996-08-27
Applicant: Jagdeep Bal , Christopher J. Bland
Inventor： Jagdeep Bal , Christopher J. Bland
CPC classification number: H03B5/366 , H03K3/0307 , H03B2200/0026 , H03B2200/005 , H03B2200/0092 , H03B2201/0266 , H03B5/364 , H03J2200/10
Abstract: The present invention provides for a voltage-controlled crystal oscillator (VCXO) which, other than the crystal itself, is full integrated. The VCXO has a pre-amplifier block, a gain stage, a first MOS transistor, a first capacitor, a second MOS transistor, and a one second capacitor. The pre-amplifier block receives an input tuning voltage and the gain stage is connected across the terminals of the oscillating crystal. The first MOS transistor and first capacitor are connected between one of the terminals of the oscillating crystal and a reference voltage. The second MOS transistor and the second capacitor are connected between the second crystal terminal and the reference voltage. The gates of both MOS transistors are connected to the output node of the pre-amplifier block. The first and second MOS transistors connect the first and second capacitors to the first and second terminals of the gain stage for a portion of the time responsive to the input tuning voltage. Thus the oscillating crystal has a load capacitance, which varies according to the input tuning voltage, so that the frequency of the VCXO varies according to the input tuning voltage.
Abstract translation: 本发明提供一种电压控制晶体振荡器（VCXO），该晶体振荡器除晶体本身之外是完全集成的。 VCXO具有前置放大器模块，增益级，第一MOS晶体管，第一电容器，第二MOS晶体管和一个第二电容器。 前置放大器模块接收输入调谐电压，并且增益级跨越振荡晶体的端子。 第一MOS晶体管和第一电容器连接在振荡晶体的一个端子和参考电压之间。 第二MOS晶体管和第二电容器连接在第二晶体端子和参考电压之间。 两个MOS晶体管的栅极连接到前置放大器模块的输出节点。 第一和第二MOS晶体管响应于输入调谐电压将第一和第二电容器连接到增益级的第一和第二端子的一部分时间。 因此，振荡晶体具有根据输入调谐电压而变化的负载电容，使得VCXO的频率根据输入调谐电压而变化。
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公开(公告)号：US5703540A
公开(公告)日：1997-12-30
申请号：US703666
申请日：1996-08-27
Applicant: Jan Gazda , Jagdeep Bal , Christopher J. Bland
Inventor： Jan Gazda , Jagdeep Bal , Christopher J. Bland
Abstract: A voltage-controlled crystal oscillator circuit with an extended range is presented. The circuit has a crystal oscillator circuit, a phase-locked loop (PLL), and a look-up table. The crystal oscillator circuit generates a signal having a frequency f.sub.ref at its output node responsive to a voltage at its input terminal. The PLL has its input node connected to the crystal oscillator output node and generates a signal at the PLL output node having a frequency f.sub.o. A first divider circuit of the PLL divides the f.sub.ref frequency by a first variable integer M and a second PLL divider circuit divides the f.sub.o frequency by a second variable integer N. The look-up table, which has comparators connected to the input terminal, a counter connected to the comparators and a memory responsive to the counter and storing M and N values, varies M and N responsive to the input terminal voltage so that the voltage-controlled crystal oscillator circuit has an increased frequency range.
Abstract translation: 提出了具有扩展范围的压控晶体振荡器电路。 该电路具有晶体振荡器电路，锁相环（PLL）和查找表。 晶体振荡器电路根据输入端的电压在其输出端产生具有频率fref的信号。 PLL的输入节点连接到晶体振荡器输出节点，并在具有频率fo的PLL输出节点处产生信号。 PLL的第一分频电路将fref频率除以第一可变整数M，第二PLL分频器电路将fo频率除以第二可变整数N.具有连接到输入端的比较器的查找表， 连接到比较器的计数器和响应于计数器并存储M和N值的存储器，响应于输入端子电压改变M和N，使得压控晶体振荡器电路具有增加的频率范围。
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