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1.发明授权
公开(公告)号：US5483486A
公开(公告)日：1996-01-09
申请号：US326654
申请日：1994-10-19
摘要： A circuit for generating one of a plurality of output voltages. The circuit includes a first conductor coupled to a first supply voltage, a second conductor coupled to a second supply voltage, a charge pump having an input and an output, a multiplexor, a first regulation circuit, and a second regulation circuit. The first regulation circuit is coupled to the first input of the multiplexor and the output of the charge pump. The first regulation circuit is for generating a first regulation voltage in response to the first supply voltage and the output of the charge pump such that the charge pump outputs a first output voltage when the first input of the multiplexor is coupled to the output of the multiplexor. The second regulation circuit is coupled to the second input of the multiplexor and the output of the charge pump. The second regulation circuit is for generating a second regulation voltage in response to the second supply voltage and the output of the charge pump such that the charge pump outputs a second output voltage when the second input of the multiplexor is coupled to the output of the multiplexor. The multiplexing of the regulation circuitry results in a reduced number of components.
摘要翻译： 一种用于产生多个输出电压之一的电路。 电路包括耦合到第一电源电压的第一导体，耦合到第二电源电压的第二导体，具有输入和输出的电荷泵，多路复用器，第一调节电路和第二调节电路。 第一调节电路耦合到多路复用器的第一输入端和电荷泵的输出端。 第一调节电路用于响应于第一电源电压和电荷泵的输出产生第一调节电压，使得当多路复用器的第一输入耦合到多路复用器的输出端时，电荷泵输出第一输出电压 。 第二调节电路耦合到多路复用器的第二输入端和电荷泵的输出端。 第二调节电路用于响应于第二电源电压和电荷泵的输出产生第二调节电压，使得当多路复用器的第二输入耦合到多路复用器的输出时，电荷泵输出第二输出电压 。 调节电路的复用导致部件数量减少。
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2.发明授权Circuitry for power supply voltage detection and system lockout for a nonvolatile memory 失效用于非易失性存储器的电源电压检测和系统锁定的电路
公开(公告)号：US5301161A
公开(公告)日：1994-04-05
申请号：US3618
申请日：1993-01-12
CPC分类号： G11C5/143 , G11C16/225 , G11C16/30
摘要： A detection circuit is described that resides in a nonvolatile memory that includes a memory array and a control circuitry coupled to the memory array for controlling operations of the memory array. The detection circuit is coupled to the control circuitry and receives a power supply for detecting potential level of the power supply and for generating a reset signal to reset the control circuitry until the potential level of the power supply rises above a predetermined level. The detection circuit includes a resistor, a first, a second, and a third transistor. The first transistor has a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node. The second transistor has a first end coupled to the first node, a second end coupled to ground, and a third end coupled to the ground. The first and second transistors function as a voltage divider. The third transistor has a first end coupled to the power supply, a second end coupled to an output node, and a third end coupled to the first node. The resistor is coupled between the output node and the ground for coupling the output node to the ground when the third transistor is not conducting, and for providing a positive potential at the output node when the third transistor is conducting. When the power supply has not reached the predetermined level, the third transistor is not conducting and the output node outputs the reset signal that is a ground potential. When the power supply rises above the predetermined level, the third transistor starts to conduct and the output node registers the positive potential and ceases generating the reset signal. The first, second, and third transistors are of the same channel type such that the circuitry operates substantially independent of process variations and temperature variations.
摘要翻译： 描述了驻留在非易失性存储器中的检测电路，其包括存储器阵列和耦合到存储器阵列的控制电路，用于控制存储器阵列的操作。 检测电路耦合到控制电路并且接收电源，用于检测电源的电位电平，并产生复位信号以复位控制电路，直到电源的电位上升到高于预定电平。 检测电路包括电阻器，第一，第二和第三晶体管。 第一晶体管具有耦合以接收电源的第一端，耦合到第一节点的第二端和耦合到第一节点的第三端。 第二晶体管具有耦合到第一节点的第一端，耦合到地的第二端和耦合到地的第三端。 第一和第二晶体管用作分压器。 第三晶体管具有耦合到电源的第一端，耦合到输出节点的第二端和耦合到第一节点的第三端。 当第三晶体管不导通时，电阻器耦合在输出节点和地之间，用于将输出节点耦合到地，并且在第三晶体管导通时在输出节点处提供正电位。 当电源尚未达到预定电平时，第三晶体管不导通，输出节点输出作为地电位的复位信号。 当电源上升到高于预定电平时，第三晶体管开始导通，输出节点寄存正电位并停止产生复位信号。 第一，第二和第三晶体管具有相同的通道类型，使得电路基本上独立于工艺变化和温度变化而工作。
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3.发明授权Flash device operating from a power-supply-in-package (PSIP) or from a power supply on chip 有权闪存设备从电源包（PSIP）或芯片上的电源供电公开(公告)号：US06639864B2
公开(公告)日：2003-10-28
申请号：US10026401
申请日：2001-12-18
IPC分类号： G11C700
摘要： A system includes a processor and a flash memory block that may receive an operating voltage sufficient for reading a memory cell. A standby oscillator may generate a first signal to a Power-Supply-In-Package block and a second, higher frequency signal to a regulator block. The first signal may control the time at which charge is stored on a first capacitor that may be used to provide charge in a standby mode to a second capacitor. The second signal may control the time at which charge is stored on the second capacitor.
摘要翻译： 系统包括处理器和闪存块，其可以接收足以读取存储器单元的工作电压。 备用振荡器可以产生到电源包装块的第一信号，以及向调节器块产生第二较高频率信号。 第一信号可以控制在第一电容器上存储电荷的时间，第一电容器可用于在待机模式下向第二电容器提供电荷。 第二信号可以控制在第二电容器上存储电荷的时间。
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公开(公告)号：US6160440A
公开(公告)日：2000-12-12
申请号：US161089
申请日：1998-09-25
CPC分类号： H02M3/073
摘要： A scaleable charge pump. The charge pump is configured on an integrated circuit device that operates at a supply voltage and includes a predetermined number of pump stages coupled in series, at least one of the stages being coupled to receive a first pumped clock signal. An output node coupled in series to one end of the predetermined number of series coupled pump stages provides a pumped output voltage.
摘要翻译： 可扩展的电荷泵。 电荷泵被配置在集成电路器件上，该集成电路器件在电源电压下工作，并且包括串联耦合的预定数量的泵级，所述级中的至少一个被耦合以接收第一泵浦时钟信号。 串联耦合到预定数量的串联耦合的泵级的一端的输出节点提供泵送的输出电压。
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公开(公告)号：US5446408A
公开(公告)日：1995-08-29
申请号：US249859
申请日：1994-05-26
摘要： An integrated circuit including an operating circuit portion which requires a predetermined voltage in order to function properly, a charge pump circuit for providing a high voltage output equal to the predetermined voltage from a lower voltage input, a terminal for receiving voltage from a source of external voltage, and a circuit for selectively providing voltage to the operating circuit portion of the integrated circuit from the terminal if the level of voltage detected at the terminal from the external voltage source is above the predetermined voltage and for providing voltage to the operating circuit portion from the output of the charge pump if the voltage detected at the terminal is less than the predetermined level.
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公开(公告)号：US5422586A
公开(公告)日：1995-06-06
申请号：US119423
申请日：1993-09-10
摘要： An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage. A first series of clock pulses is applied to the gate terminals of the first switching transistor devices in every other stage of the charge pump and to the gate terminals of the second control transistor devices in stages between; and a second series of clock pulses which do not overlap the first series of clock pulses is applied to the gate terminals of the first switching transistor devices in alternate stages of the charge pump and to the gate terminals of the second control transistor devices in stages between the alternate stages. These pulses cause the switching transistor to switch on and off in alternate stages in a manner that the gate terminal goes higher than the drain terminal so that charge is transferred without threshold drop between stages and high current as well as high voltage is pumped to the output terminal.
摘要翻译： 包括多级的集成电路电荷泵电路，每级包括具有与所有其它级的源极和漏极端子串联连接的源极和漏极端子的第一N型场效应开关晶体管器件，第二N型场效应控制 具有连接第一开关晶体管器件的漏极端子和栅极端子的漏极和源极端子的晶体管器件和连接到第一器件的源极端子的存储电容器; 要被泵送的电压源连接到第一级的第一器件的漏极端子。 第一系列时钟脉冲被施加到电荷泵的每隔一级的第一开关晶体管器件的栅极端子和第二控制晶体管器件的栅极端子之间; 并且不与第一系列时钟脉冲重叠的第二系列时钟脉冲在电荷泵的交替级中施加到第一开关晶体管器件的栅极端子，并且在第二组控制晶体管器件的栅极端子之间分阶段地施加 替代阶段。 这些脉冲使得开关晶体管以交替的方式导通和截止，使得栅极端子比漏极端子高，使得电荷在级之间没有阈值下降而被传送，并且高电压被泵送到输出端 终奌站。
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公开(公告)号：USRE42551E1
公开(公告)日：2011-07-12
申请号：US10094056
申请日：2002-03-07
申请人： Vishram Prakash Dalvi , Rodney R. Rozman , Christopher John Haid , Jerry Kreifels , Joseph Tsang , Jeff Evertt , Jahanshir J. Javanifard , Jeffrey J. Peterson
发明人： Vishram Prakash Dalvi , Rodney R. Rozman , Christopher John Haid , Jerry Kreifels , Joseph Tsang , Jeff Evertt , Jahanshir J. Javanifard , Jeffrey J. Peterson
IPC分类号： H04L9/32
CPC分类号： G06F12/1433 , G11C16/22
摘要： A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.
摘要翻译： 包括第一存储器阵列，耦合到第一存储器阵列的控制电路和耦合到控制电路的第二独立存储器阵列的闪速存储器件。 第一存储器阵列包括多个存储块，每个存储块具有存储单元。 存储单元可以是非易失性闪存单元。 控制电路控制存储单元的编程，擦除和读取。 第二存储器阵列包括多个块锁定位，每个块锁定位对应于多个存储块中的一个。 每个块锁定位的状态指示对应的存储器块中的存储器单元是否被锁定。 第二存储器阵列还可以包括指示块锁定位是否被锁定的主锁定位。
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8.发明授权Variable voltage source for a flash device operating from a power-supply-in-package (PSIP) 失效从电源包（PSIP）操作的闪存设备的可变电压源公开(公告)号：US06614210B2
公开(公告)日：2003-09-02
申请号：US10026593
申请日：2001-12-18
IPC分类号： H02J312
CPC分类号： H02M3/157 , G11C16/30 , H02M2001/0032 , Y02B70/16
摘要： A system includes a processor and a flash memory block that may receive an operating voltage potential sufficient for reading a memory cell. A Power-Supply-In-Package (PSIP) block may adjust a supply voltage in accordance with received data values and be used to power the flash memory block.
摘要翻译： 系统包括处理器和闪存块，其可以接收足以读取存储器单元的工作电压。 电源包装（PSIP）块可以根据接收的数据值调整电源电压，并用于为闪存块供电。
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公开(公告)号：US06567763B1
公开(公告)日：2003-05-20
申请号：US09474835
申请日：1999-12-30
申请人： Jahanshir J. Javanifard , Steve Wells , Hari Giduturi , Dave Ward
发明人： Jahanshir J. Javanifard , Steve Wells , Hari Giduturi , Dave Ward
IPC分类号： G01K700
CPC分类号： G01K7/01
摘要： A temperature measurement device includes at least one constant current generator to provide a first current and a second current to a temperature sensor, and a signal processing element to provide an analog output signal corresponding to a temperature of the temperature sensor based on a difference between a first voltage of the temperature sensor at the first current and a second voltage of the temperature sensor at the second current.
摘要翻译： 温度测量装置包括至少一个恒定电流发生器，以向温度传感器提供第一电流和第二电流;以及信号处理元件，用于根据温度传感器的差异提供对应于温度传感器的温度的模拟输出信号 在第一电流下温度传感器的第一电压和在第二电流下温度传感器的第二电压。
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公开(公告)号：US6035401A
公开(公告)日：2000-03-07
申请号：US794283
申请日：1997-02-03
申请人： Vishram Prakash Dalvi , Rodney R. Rozman , Christopher John Haid , Jerry Kreifels , Joseph Tsang , Jeff Evertt , Jahanshir J. Javanifard , Jeffrey J. Peterson
发明人： Vishram Prakash Dalvi , Rodney R. Rozman , Christopher John Haid , Jerry Kreifels , Joseph Tsang , Jeff Evertt , Jahanshir J. Javanifard , Jeffrey J. Peterson
CPC分类号： G06F12/1433 , G11C16/22
摘要： A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.
摘要翻译： 包括第一存储器阵列，耦合到第一存储器阵列的控制电路和耦合到控制电路的第二独立存储器阵列的闪速存储器件。 第一存储器阵列包括多个存储块，每个存储块具有存储单元。 存储单元可以是非易失性闪存单元。 控制电路控制存储单元的编程，擦除和读取。 第二存储器阵列包括多个块锁定位，每个块锁定位对应于多个存储块中的一个。 每个块锁定位的状态指示对应的存储器块中的存储器单元是否被锁定。 第二存储器阵列还可以包括指示块锁定位是否被锁定的主锁定位。
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