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公开(公告)号：US06255896B1
公开(公告)日：2001-07-03
申请号：US09406329
申请日：1999-09-27
申请人： Bo Li , Marc E. Landgraf , Mase Taub , Sandeep K. Guliani
发明人： Bo Li , Marc E. Landgraf , Mase Taub , Sandeep K. Guliani
IPC分类号： G05F302
CPC分类号： H02M3/073
摘要： The present invention provides a method, apparatus, and system for rapid transition of a charge pump circuit from a low power state to a high power state. The charge pump circuit has at least one pump stage. The at least one pump stage includes at least a first capacitor coupled to a gate of a first switching transistor forming a boot node and at least a second capacitor coupled to an output node of the at least one pump stage. It is determined whether the charge pump circuit is in the low power state or the high power state. If the charge pump circuit is in the low power state, a first predetermined voltage and a second predetermined voltage that are different than the ground voltage level are applied to the boot node and the output node, respectively. If the charge pump circuit is in the high power state, the first predetermined voltage and the second predetermined voltage are removed from the boot node and the output node, respectively.
摘要翻译： 本发明提供了一种用于将电荷泵电路从低功率状态快速转变到高功率状态的方法，装置和系统。 电荷泵电路具有至少一个泵级。 所述至少一个泵级包括耦合到形成引导节点的第一开关晶体管的栅极的至少第一电容器和耦合到所述至少一个泵级的输出节点的至少第二电容器。 确定电荷泵电路是处于低功率状态还是处于高功率状态。 如果电荷泵电路处于低功率状态，则分别将不同于接地电压电平的第一预定电压和第二预定电压施加到引导节点和输出节点。 如果电荷泵电路处于高功率状态，则分别从引导节点和输出节点去除第一预定电压和第二预定电压。
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2.发明授权
公开(公告)号：US5483486A
公开(公告)日：1996-01-09
申请号：US326654
申请日：1994-10-19
摘要： A circuit for generating one of a plurality of output voltages. The circuit includes a first conductor coupled to a first supply voltage, a second conductor coupled to a second supply voltage, a charge pump having an input and an output, a multiplexor, a first regulation circuit, and a second regulation circuit. The first regulation circuit is coupled to the first input of the multiplexor and the output of the charge pump. The first regulation circuit is for generating a first regulation voltage in response to the first supply voltage and the output of the charge pump such that the charge pump outputs a first output voltage when the first input of the multiplexor is coupled to the output of the multiplexor. The second regulation circuit is coupled to the second input of the multiplexor and the output of the charge pump. The second regulation circuit is for generating a second regulation voltage in response to the second supply voltage and the output of the charge pump such that the charge pump outputs a second output voltage when the second input of the multiplexor is coupled to the output of the multiplexor. The multiplexing of the regulation circuitry results in a reduced number of components.
摘要翻译： 一种用于产生多个输出电压之一的电路。 电路包括耦合到第一电源电压的第一导体，耦合到第二电源电压的第二导体，具有输入和输出的电荷泵，多路复用器，第一调节电路和第二调节电路。 第一调节电路耦合到多路复用器的第一输入端和电荷泵的输出端。 第一调节电路用于响应于第一电源电压和电荷泵的输出产生第一调节电压，使得当多路复用器的第一输入耦合到多路复用器的输出端时，电荷泵输出第一输出电压 。 第二调节电路耦合到多路复用器的第二输入端和电荷泵的输出端。 第二调节电路用于响应于第二电源电压和电荷泵的输出产生第二调节电压，使得当多路复用器的第二输入耦合到多路复用器的输出时，电荷泵输出第二输出电压 。 调节电路的复用导致部件数量减少。
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3.发明授权Circuitry for power supply voltage detection and system lockout for a nonvolatile memory 失效用于非易失性存储器的电源电压检测和系统锁定的电路
公开(公告)号：US5301161A
公开(公告)日：1994-04-05
申请号：US3618
申请日：1993-01-12
CPC分类号： G11C5/143 , G11C16/225 , G11C16/30
摘要： A detection circuit is described that resides in a nonvolatile memory that includes a memory array and a control circuitry coupled to the memory array for controlling operations of the memory array. The detection circuit is coupled to the control circuitry and receives a power supply for detecting potential level of the power supply and for generating a reset signal to reset the control circuitry until the potential level of the power supply rises above a predetermined level. The detection circuit includes a resistor, a first, a second, and a third transistor. The first transistor has a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node. The second transistor has a first end coupled to the first node, a second end coupled to ground, and a third end coupled to the ground. The first and second transistors function as a voltage divider. The third transistor has a first end coupled to the power supply, a second end coupled to an output node, and a third end coupled to the first node. The resistor is coupled between the output node and the ground for coupling the output node to the ground when the third transistor is not conducting, and for providing a positive potential at the output node when the third transistor is conducting. When the power supply has not reached the predetermined level, the third transistor is not conducting and the output node outputs the reset signal that is a ground potential. When the power supply rises above the predetermined level, the third transistor starts to conduct and the output node registers the positive potential and ceases generating the reset signal. The first, second, and third transistors are of the same channel type such that the circuitry operates substantially independent of process variations and temperature variations.
摘要翻译： 描述了驻留在非易失性存储器中的检测电路，其包括存储器阵列和耦合到存储器阵列的控制电路，用于控制存储器阵列的操作。 检测电路耦合到控制电路并且接收电源，用于检测电源的电位电平，并产生复位信号以复位控制电路，直到电源的电位上升到高于预定电平。 检测电路包括电阻器，第一，第二和第三晶体管。 第一晶体管具有耦合以接收电源的第一端，耦合到第一节点的第二端和耦合到第一节点的第三端。 第二晶体管具有耦合到第一节点的第一端，耦合到地的第二端和耦合到地的第三端。 第一和第二晶体管用作分压器。 第三晶体管具有耦合到电源的第一端，耦合到输出节点的第二端和耦合到第一节点的第三端。 当第三晶体管不导通时，电阻器耦合在输出节点和地之间，用于将输出节点耦合到地，并且在第三晶体管导通时在输出节点处提供正电位。 当电源尚未达到预定电平时，第三晶体管不导通，输出节点输出作为地电位的复位信号。 当电源上升到高于预定电平时，第三晶体管开始导通，输出节点寄存正电位并停止产生复位信号。 第一，第二和第三晶体管具有相同的通道类型，使得电路基本上独立于工艺变化和温度变化而工作。
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4.发明授权Preventing data corruption in a memory device using a modified memory cell conditioning methodology 失效使用修改的存储器单元调节方法防止存储器件中的数据损坏公开(公告)号：US06212099B1
公开(公告)日：2001-04-03
申请号：US09378306
申请日：1999-08-20
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/08 , G11C16/3418
摘要： An embodiment of the invention is directed to a method of operating a flash memory, which includes discharging at least one local wordline of an unselected block of flash memory cells during an interval in which a selected set of flash memory cells are being conditioned, such that the at least one local wordline does not develop a charge that is sufficient to corrupt the data stored in the unselected block.
摘要翻译： 本发明的实施例涉及一种操作闪速存储器的方法，其包括在所选择的一组闪存单元被调节的间隔期间，对闪存单元的未选择块的至少一个本地字线进行放电，使得 至少一个本地字线不产生足以破坏存储在未选择块中的数据的电荷。
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5.发明授权Circuitry and method for selecting a drain programming voltage for a nonvolatile memory 失效用于选择非易失性存储器的漏极编程电压的电路和方法
公开(公告)号：US5402370A
公开(公告)日：1995-03-28
申请号：US119738
申请日：1993-09-10
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/30 , G11C16/34 , G11C29/02 , G11C29/50 , G11C7/00
CPC分类号： G11C29/021 , G11C16/30 , G11C16/34 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C16/04 , G11C2029/5004
摘要： A nonvolatile memory residing on a single substrate is described. The nonvolatile memory includes a memory array having at least a memory cell. The memory cell includes a drain region, a source region, a control gate, and a floating gate. A drain programming voltage generation circuit is coupled to a programming voltage source and the drain region of the memory cell for providing a drain programming voltage to the drain region of the memory cell during programming of the memory cell. A control circuit is coupled to the drain programming voltage generation circuit for causing the drain programming voltage to vary with respect to a programming ability of the memory cell such that the memory cell is programmed to be within a predetermined range of a predetermined threshold voltage with a predetermined gate programming voltage for a predetermined programming time. A method for setting the drain programming voltage for the nonvolatile memory such that the drain programming voltage varies inversely with respect to the programming ability of the nonvolatile memory is also described.
摘要翻译： 描述驻留在单个基板上的非易失性存储器。 非易失性存储器包括具有至少存储单元的存储器阵列。 存储单元包括漏极区域，源极区域，控制栅极和浮动栅极。 漏极编程电压产生电路耦合到编程电压源和存储单元的漏极区域，用于在存储器单元的编程期间向漏极区域提供漏极编程电压。 控制电路耦合到漏极编程电压产生电路，用于使漏极编程电压相对于存储器单元的编程能力而变化，使得存储器单元被编程在预定阈值电压的预定范围内，其中 预定的编程电压用于预定的编程时间。 还描述了一种用于设置非易失性存储器的漏极编程电压的方法，使得漏极编程电压相对于非易失性存储器的编程能力反向变化。
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