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1.发明授权Circuitry for power supply voltage detection and system lockout for a nonvolatile memory 失效用于非易失性存储器的电源电压检测和系统锁定的电路
公开(公告)号：US5301161A
公开(公告)日：1994-04-05
申请号：US3618
申请日：1993-01-12
CPC分类号： G11C5/143 , G11C16/225 , G11C16/30
摘要： A detection circuit is described that resides in a nonvolatile memory that includes a memory array and a control circuitry coupled to the memory array for controlling operations of the memory array. The detection circuit is coupled to the control circuitry and receives a power supply for detecting potential level of the power supply and for generating a reset signal to reset the control circuitry until the potential level of the power supply rises above a predetermined level. The detection circuit includes a resistor, a first, a second, and a third transistor. The first transistor has a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node. The second transistor has a first end coupled to the first node, a second end coupled to ground, and a third end coupled to the ground. The first and second transistors function as a voltage divider. The third transistor has a first end coupled to the power supply, a second end coupled to an output node, and a third end coupled to the first node. The resistor is coupled between the output node and the ground for coupling the output node to the ground when the third transistor is not conducting, and for providing a positive potential at the output node when the third transistor is conducting. When the power supply has not reached the predetermined level, the third transistor is not conducting and the output node outputs the reset signal that is a ground potential. When the power supply rises above the predetermined level, the third transistor starts to conduct and the output node registers the positive potential and ceases generating the reset signal. The first, second, and third transistors are of the same channel type such that the circuitry operates substantially independent of process variations and temperature variations.
摘要翻译： 描述了驻留在非易失性存储器中的检测电路，其包括存储器阵列和耦合到存储器阵列的控制电路，用于控制存储器阵列的操作。 检测电路耦合到控制电路并且接收电源，用于检测电源的电位电平，并产生复位信号以复位控制电路，直到电源的电位上升到高于预定电平。 检测电路包括电阻器，第一，第二和第三晶体管。 第一晶体管具有耦合以接收电源的第一端，耦合到第一节点的第二端和耦合到第一节点的第三端。 第二晶体管具有耦合到第一节点的第一端，耦合到地的第二端和耦合到地的第三端。 第一和第二晶体管用作分压器。 第三晶体管具有耦合到电源的第一端，耦合到输出节点的第二端和耦合到第一节点的第三端。 当第三晶体管不导通时，电阻器耦合在输出节点和地之间，用于将输出节点耦合到地，并且在第三晶体管导通时在输出节点处提供正电位。 当电源尚未达到预定电平时，第三晶体管不导通，输出节点输出作为地电位的复位信号。 当电源上升到高于预定电平时，第三晶体管开始导通，输出节点寄存正电位并停止产生复位信号。 第一，第二和第三晶体管具有相同的通道类型，使得电路基本上独立于工艺变化和温度变化而工作。
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2.发明授权Microprocessor system including first and second nonvolatile memory arrays which may be simultaneously read and reprogrammed 失效微处理器系统包括可以同时读取和重新编程的第一和第二非易失性存储器阵列
公开(公告)号：US5361343A
公开(公告)日：1994-11-01
申请号：US60828
申请日：1993-05-10
CPC分类号： G11C16/10 , G11C7/00 , G11C2216/22
摘要： A microprocessor system includes a central processing unit (CPU) and a nonvolatile memory having a first memory array and a second memory array. A first address register is provided for storing a first address for the first memory array. A second address register is provided for storing a second address for the second memory array. Array select circuitry responsive to an incoming address is provided for selecting the first memory array for a reprogramming operation and the second memory array for a read operation. A multiplexer has inputs coupled to the first memory array and the second memory array for selectively coupling one of the first memory array and the second memory array to an output of the memory. The array select circuitry directs the first address to the first memory array and the second address to the second memory array. The array select circuitry controls the multiplexer to couple the second memory array to the output during the reprogramming operation of the first memory array. The memory further includes a write state machine for controlling reprogramming of the memory. The write state machine allows write automation of the nonvolatile memory.
摘要翻译： 微处理器系统包括中央处理单元（CPU）和具有第一存储器阵列和第二存储器阵列的非易失性存储器。 提供第一地址寄存器用于存储第一存储器阵列的第一地址。 提供第二地址寄存器用于存储第二存储器阵列的第二地址。 响应于输入地址的阵列选择电路被提供用于选择用于重新编程操作的第一存储器阵列和用于读取操作的第二存储器阵列。 多路复用器具有耦合到第一存储器阵列和第二存储器阵列的输入，用于选择性地将第一存储器阵列和第二存储器阵列之一耦合到存储器的输出。 阵列选择电路将第一地址指向第一存储器阵列，将第二地址指向第二存储器阵列。 阵列选择电路控制多路复用器在第一存储器阵列的重新编程操作期间将第二存储器阵列耦合到输出。 存储器还包括用于控制存储器的重新编程的写状态机。 写状态机允许非易失性存储器的写入自动化。
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3.发明授权Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array 失效用于使用易失性存储器传送数据以缓冲非易失性存储器阵列的数据的集成电路存储器和方法公开(公告)号：US06418506B1
公开(公告)日：2002-07-09
申请号：US08777898
申请日：1996-12-31
IPC分类号： G06F1300
CPC分类号： G11C11/005
摘要： An integrated circuit (IC) memory device having an interface coupled with a volatile random access memory (RAM) array and a nonvolatile flash memory array. Data to be written from an external device to the IC memory device is initially written to the volatile RAM array to provide for fast execution of a write operation, and is then written from the volatile RAM array to the nonvolatile flash memory array via the interface in a manner that is relatively transparent to external devices and the user. The interface may be configured to transfer data from the volatile RAM array to the external device if a read request matches an address tag field stored in the volatile RAM array. Data from first and second block addresses in the volatile RAM array and flash memory array may be merged in a flash merge buffer, and validity bits may be used to ensure that potentially stale data in the flash memory array is not used and that data coherency is maintained. Data may also be simultaneously written to or read from the volatile RAM array during at least a portion of the time in which data is being read from or written to the flash memory array. A check may be made to ensure that the flash merge buffer is empty before reading data from the flash memory array.
摘要翻译： 具有与易失性随机存取存储器（RAM）阵列和非易失性闪存阵列耦合的接口的集成电路（IC）存储器件。 要从外部设备写入IC存储器件的数据最初被写入易失性RAM阵列以提供写入操作的快速执行，然后通过该接口从易失性RAM阵列写入非易失性闪存阵列 一种对外部设备和用户相对透明的方式。 如果读取请求与存储在易失性RAM阵列中的地址标签字段相匹配，则该接口可被配置为将数据从易失性RAM阵列传送到外部设备。 来自易失性RAM阵列和闪速存储器阵列中的第一和第二块地址的数据可以合并到闪存合并缓冲器中，并且可以使用有效位来确保不使用闪存阵列中潜在的过时数据，并且数据一致性是 保持。 在数据被读取或写入闪速存储器阵列的时间的至少一部分期间，数据也可以被同时写入或从易失性RAM阵列读取。 在从闪存阵列读取数据之前，可以进行检查以确保闪存合并缓冲区为空。
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公开(公告)号：US5621690A
公开(公告)日：1997-04-15
申请号：US430344
申请日：1995-04-28
申请人： Owen W. Jungroth , Mark D. Winston
发明人： Owen W. Jungroth , Mark D. Winston
CPC分类号： G11C29/808 , G11C16/08 , G11C29/82 , G11C8/12
摘要： A nonvolatile memory includes a global line. A plurality of memory blocks and a redundant block are also included in the memory, each block having a plurality of local lines and a decoder for selectively connecting the global line to one of the local lines when the decoder is enabled and for isolating the local lines from the global line when the decoder is disabled. When one of the plurality of blocks is found to be a defective block, the defective block is replaced by the redundant block. Circuitry is provided for disabling the decoder of the defective block and enabling the decoder of the redundant block whenever the defective block is addressed.
摘要翻译： 非易失性存储器包括全局线。 多个存储器块和冗余块也包括在存储器中，每个块具有多个本地线和解码器，用于当解码器被使能时有选择地将全局线连接到本地线之一并且用于隔离本地线 当解码器被禁用时，从全局线路。 当发现多个块中的一个是缺陷块时，由冗余块替换缺陷块。 提供了电路，用于禁用故障块的解码器，并且每当有缺陷块被寻址时，使能冗余块的解码器。
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公开(公告)号：US5245572A
公开(公告)日：1993-09-14
申请号：US738179
申请日：1991-07-30
CPC分类号： G11C16/10 , G11C7/00 , G11C2216/22
摘要： A floating gate nonvolatile memory. The memory includes a first memory array and a second memory array. A first address register is provided for storing a first address for the first memory array. A second address register is provided for storing a second address for the second memory array. A multiplexer is coupled to the first memory array and the second memory array at one end and an output of the memory device at the other end for selectively coupling one of the first memory array and the second memory array to the output at a time. Array select circuitry responsive to an incoming address is provided for selecting the first memory array for a reprogramming operation and the second memory array for a read operation. The array select circuitry directs the first address to the first address register and the second address to the second address register. The array select circuitry controls the multiplexer for coupling the second memory array to the output during the reprogramming operation of the first memory array.
摘要翻译： 浮动非易失性存储器。 存储器包括第一存储器阵列和第二存储器阵列。 提供第一地址寄存器用于存储第一存储器阵列的第一地址。 提供第二地址寄存器用于存储第二存储器阵列的第二地址。 多路复用器在一端被耦合到第一存储器阵列和第二存储器阵列，另一端耦合到存储器件的输出端，用于选择性地将第一存储器阵列和第二存储器阵列之一一次耦合到输出。 响应于输入地址的阵列选择电路被提供用于选择用于重新编程操作的第一存储器阵列和用于读取操作的第二存储器阵列。 阵列选择电路将第一个地址指向第一个地址寄存器，第二个地址指向第二个地址寄存器。 阵列选择电路控制多路复用器，用于在第一存储器阵列的重新编程操作期间将第二存储器阵列耦合到输出。
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