公开(公告)号：US08336008B2

公开(公告)日：2012-12-18

申请号：US12569421

申请日：2009-09-29

申请人： James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

发明人： James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Mechanisms are provided for characterizing long range variability in integrated circuit manufacturing. A model derivation component tests one or more density pattern samples, which are a fabricated integrated circuits having predetermined pattern densities and careful placement of current-voltage (I-V) sensors. The model derivation component generates one or more empirical models to establish range of influence of long range variability effects in the density pattern sample. A variability analysis component receives an integrated circuit design and, using the one or more empirical models, analyzes the integrated circuit design to isolate possible long range variability effects in the integrated circuit design.

摘要翻译： 提供了用于表征集成电路制造中的长距离变化的机制。 模型推导部件测试一个或多个密度样本样本，其是具有预定图案密度的制造的集成电路和电流 - 电压（I-V）传感器的仔细放置。 模型推导组件产生一个或多个经验模型，以确定密度模式样本中长距离变异效应的影响范围。 可变性分析组件接收集成电路设计，并且使用一个或多个经验模型分析集成电路设计以隔离集成电路设计中的可能的长距离变化效应。

公开(公告)号：US20110078641A1

公开(公告)日：2011-03-31

申请号：US12569421

申请日：2009-09-29

申请人： James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

发明人： James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Mechanisms are provided for characterizing long range variability in integrated circuit manufacturing. A model derivation component tests one or more density pattern samples, which are a fabricated integrated circuits having predetermined pattern densities and careful placement of current-voltage (I-V) sensors. The model derivation component generates one or more empirical models to establish range of influence of long range variability effects in the density pattern sample. A variability analysis component receives an integrated circuit design and, using the one or more empirical models, analyzes the integrated circuit design to isolate possible long range variability effects in the integrated circuit design.

摘要翻译： 提供了用于表征集成电路制造中的长距离变化的机制。 模型推导部件测试一个或多个密度样本样本，其是具有预定图案密度的制造的集成电路和电流 - 电压（I-V）传感器的仔细放置。 模型推导组件产生一个或多个经验模型，以确定密度模式样本中长距离变异效应的影响范围。 可变性分析组件接收集成电路设计，并且使用一个或多个经验模型分析集成电路设计以隔离集成电路设计中的可能的长距离变化效应。

公开(公告)号：US20100327892A1

公开(公告)日：2010-12-30

申请号：US12492619

申请日：2009-06-26

申请人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

发明人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

IPC分类号： G01R31/02

CPC分类号： G01R31/2858

摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

摘要翻译： 提供了一种用于恒流电迁移应力测试的并行阵列架构。 并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。 该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。 此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分 电流源逻辑。 使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

公开(公告)号：US07834649B2

公开(公告)日：2010-11-16

申请号：US12779038

申请日：2010-05-12

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US20100225348A1

公开(公告)日：2010-09-09

申请号：US12779038

申请日：2010-05-12

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US07782076B2

公开(公告)日：2010-08-24

申请号：US12141862

申请日：2008-06-18

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

公开(公告)号：US07397259B1

公开(公告)日：2008-07-08

申请号：US11736146

申请日：2007-04-17

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26 ,  G01R33/00 ,  G01R31/02

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columnns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线进行操作的输入/输出引脚。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US08217671B2

公开(公告)日：2012-07-10

申请号：US12492619

申请日：2009-06-26

申请人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

发明人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

IPC分类号： G01R31/00

CPC分类号： G01R31/2858

摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

摘要翻译： 提供了一种用于恒流电迁移应力测试的并行阵列架构。 并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。 该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。 此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分 电流源逻辑。 使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

公开(公告)号：US20080284460A1

公开(公告)日：2008-11-20

申请号：US12141862

申请日：2008-06-18

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/36

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US11246568B2

公开(公告)日：2022-02-15

申请号：US16393976

申请日：2019-04-25

申请人： Ying Liu

发明人： Ying Liu

IPC分类号： B06B1/06 ,  H01L41/04 ,  A61B8/00 ,  A61B8/14 ,  B06B1/02 ,  B06B3/00 ,  G10K11/34 ,  G01S15/89 ,  H01H89/00 ,  H01G2/00 ,  H01G9/28 ,  H01L41/113

摘要： A circuit for 3D ultrasound imaging systems includes multiple sensor units, multiple unit circuits and multiple row sharing circuits. The unit circuits are connected with the sensor units respectively. Each row of unit circuits share a row sharing circuit. Each unit circuit includes a first electrically controlled switch, a second electrically controlled switch and a control circuit. Each row sharing circuit includes a signal transmission bus, a signal receiving bus and a row main control circuit. The signal transmission bus and the signal receiving bus of each row sharing circuit extend through a corresponding row of unit circuits. The row main control circuit of each row is configured to transmit main control signals, transmission control signals and receiving control signals to a corresponding row of unit circuits so as to select the corresponding sensor units to transmit or receive ultrasound signals.