-
公开(公告)号：US06976128B1
公开(公告)日：2005-12-13
申请号：US10255420
申请日：2002-09-26
CPC分类号： G06F9/30047 , G06F12/0804 , G06F12/127
摘要： A system and method is provided to selectively flush data from cache memory to a main memory irrespective of the replacement algorithm that is used to manage the cache data. According to one aspect of the invention, novel “page flush” and “cache line flush” instructions are provided to flush a page and a cache line of memory data, respectively, from a cache to a main memory. In one embodiment, these instructions are included within the hardware instruction set of an Instruction Processor (IP). According to another aspect of the invention, flush operations are initiated using a background interface that interconnects the IP with its associated cache memory. A primary interface that also interconnects the IP to the cache memory is used to simultaneously issue higher-priority requests so that processor throughput is increased.
摘要翻译： 提供了一种系统和方法，用于选择性地将数据从高速缓存存储器刷新到主存储器，而与用于管理高速缓存数据的替换算法无关。 根据本发明的一个方面，提供了新颖的“页面刷新”和“高速缓存行刷新”指令，用于将存储器数据的页面和高速缓存行分别从缓存刷新到主存储器。 在一个实施例中，这些指令被包括在指令处理器（IP）的硬件指令集中。 根据本发明的另一方面，使用将IP与其相关联的高速缓冲存储器互连的后台接口来启动刷新操作。 也将IP与高速缓冲存储器互连的主界面用于同时发出较高优先级的请求，从而提高处理器吞吐量。
-
公开(公告)号：US06993630B1
公开(公告)日：2006-01-31
申请号：US10255393
申请日：2002-09-26
申请人： James A. Williams , Robert H. Andrighetti , Conrad S. Shimada , Donald C. Englin , Kelvin S. Vartti
发明人： James A. Williams , Robert H. Andrighetti , Conrad S. Shimada , Donald C. Englin , Kelvin S. Vartti
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache. Predetermined ones of the requests are provided to pre-fetch control logic, which determines whether the data signals are available within the cache. If not, the data signals are retrieved from another memory within the data processing system, and are stored to the cache. According to one aspect, the rate at which pre-fetch requests are generated may be programmably selected to match the rate at which the associated requests to access the data signals are provided to the cache. In another embodiment, pre-fetch control logic receives information to generate pre-fetch requests using a dedicated interface coupling the pre-fetch control logic to the IP.
摘要翻译： 公开了一种用于预取数据信号的系统和方法。 根据本发明的一个方面，指令处理器（IP）产生访问高速缓存内的数据信号的请求。 将预定的请求提供给预取控制逻辑，其确定数据信号是否在高速缓存内可用。 如果不是，数据信号从数据处理系统中的另一个存储器检索，并被存储到高速缓存。 根据一个方面，可以可编程地选择生成预取请求的速率以匹配将相关联的数据信号请求提供给高速缓存的速率。 在另一个实施例中，预取控制逻辑接收信息以使用将预取控制逻辑耦合到IP的专用接口来生成预取请求。
-
公开(公告)号：US07356647B1
公开(公告)日：2008-04-08
申请号：US11209227
申请日：2005-08-23
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F12/0817
摘要： A cache arrangement of a data processing system provides a cache flush operation initiated by a command from a maintenance processor. The cache arrangement includes a cache memory, a mode register, and a controller. The mode register is settable by the maintenance processor to one of first and second values. The controller selectively writes all of the modified information in the cache memory to the system memory responsive to the command. Also in response to this command, all of the information is invalidated in the cache memory if the mode register is set to the second value. In one embodiment, none of the information except the modified data is invalidated if the mode register is set to the first value. The second value may be utilized to efficiently reassign one or more cache memories to a new partition.
摘要翻译： 数据处理系统的缓存布置提供由维护处理器的命令发起的高速缓存刷新操作。 高速缓存装置包括高速缓冲存储器，模式寄存器和控制器。 模式寄存器可由维护处理器设置为第一和第二值之一。 控制器响应于该命令选择性地将高速缓冲存储器中的所有修改的信息写入系统存储器。 此外，响应于该命令，如果模式寄存器被设置为第二值，则所有信息在高速缓冲存储器中被无效。 在一个实施例中，如果模式寄存器被设置为第一值，则除了修改的数据之外的信息都不会失效。 可以利用第二值来有效地将一个或多个高速缓冲存储器重新分配到新的分区。
-
公开(公告)号：US07356650B1
公开(公告)日：2008-04-08
申请号：US11156225
申请日：2005-06-17
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0811
摘要： Systems and methods are provided for a data processing system and a cache arrangement. The data processing system includes at least one processor, a first-level cache, a second-level cache, and a memory arrangement. The first-level cache bypasses storing data for a memory request when a do-not-cache attribute is associated with the memory request. The second-level cache stores the data for the memory request. The second-level cache also bypasses updating of least-recently-used indicators of the second-level cache when the do-not-cache attribute is associated with the memory request.
摘要翻译： 为数据处理系统和缓存装置提供了系统和方法。 数据处理系统包括至少一个处理器，第一级高速缓存，二级高速缓存和存储器布置。 当不高速缓存属性与存储器请求相关联时，第一级缓存绕过存储器请求的存储数据。 第二级缓存存储用于存储器请求的数据。 当不高速缓存属性与存储器请求相关联时，二级缓存也绕过二级缓存的最近最少使用的指示符的更新。
-
5.发明授权System and method for maintaining memory coherency within a multi-processor data processing system 有权用于在多处理器数据处理系统内维持存储器一致性的系统和方法公开(公告)号：US07065614B1
公开(公告)日：2006-06-20
申请号：US10600880
申请日：2003-06-20
CPC分类号： G06F12/0817
摘要： The current invention provides a system and method for maintaining memory coherency within a multiprocessor environment that includes multiple requesters such as instruction processors coupled to a shared main memory. Within the system of the current invention, data may be provided from the shared memory to a requester for update purposes before all other read-only copies of this data stored elsewhere within the system have been invalidated. To ensure that this acceleration mechanism does not result in memory incoherency, an instruction is provided for inclusion within the instruction set of the processor. Execution of this instruction causes the executing processor to discontinue execution until all outstanding invalidation activities have completed for any data that has been retrieved and updated by the processor.
摘要翻译： 本发明提供了一种用于在多处理器环境内维持存储器一致性的系统和方法，所述多处理器环境包括多个请求者，例如耦合到共享主存储器的指令处理器。 在本发明的系统内，在系统内其他地方存储的该数据的所有其它只读副本已被无效之前，可以从共享存储器向请求者提供数据用于更新目的。 为了确保这种加速机制不会导致内存不连续性，提供了用于包含在处理器的指令集内的指令。 该指令的执行将导致执行处理器停止执行，直到所有未完成的无效活动已经完成，处理器已检索和更新的任何数据。
-
公开(公告)号：US07120836B1
公开(公告)日：2006-10-10
申请号：US09707625
申请日：2000-11-07
申请人： Donald C. Englin , Kelvin S. Vartti
发明人： Donald C. Englin , Kelvin S. Vartti
IPC分类号： G06F11/00
CPC分类号： G06F12/0802 , G06F11/1064 , G11C15/00 , G11C2029/0411
摘要： A system and method for increasing computing throughput through execution of parallel data error detection/correction and cache hit detection operations. In one path, hit detection occurs independent of and concurrent with error detection and correction operations, and reliance on hit detection in this path is based on the absence of storage errors. A single error correction code (ECC) is used to minimize storage requirements, and data hit comparisons based on the cached address and requested address are performed exclusive of ECC bits to minimize bit comparison requirements.
摘要翻译： 一种用于通过执行并行数据错误检测/校正和高速缓存命中检测操作来增加计算吞吐量的系统和方法。 在一个路径中，命中检测与错误检测和校正操作无关并发，并且依赖于该路径中的命中检测是基于不存在存储错误的。 使用单个纠错码（ECC）来最小化存储要求，并且基于缓存的地址和请求的地址的数据命中比较被排除在ECC位之外以最小化比特比较要求。
-
公开(公告)号：US06868482B1
公开(公告)日：2005-03-15
申请号：US09506038
申请日：2000-02-17
CPC分类号： G06F12/0804 , G06F12/0811 , G06F12/0891
摘要： Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory. The flush apparatus uses these two indicators to transfer all cache lines that are within the remote memory address range and have been modified, back to the remote memory prior to dynamically removing the local cache resources due to either system maintenance or dynamic partitioning.
摘要翻译： 每个双重多处理系统具有多个处理器，每个处理器具有通过缓存的第一级写入到第二级缓存的存储。 第三级存储器由双系统共享，第一级和第二级高速缓存可全局寻址到所有第三级存储器。 处理器可以写入本地二级缓存，并通过本地存储控制器访问远程二级缓存。 双系统的一致性方案为每个二级缓存提供每个高速缓存行的指示符，其中显示哪些是有效的，哪些已被修改或不同于相应的第三级存储器中反映的指示。 冲洗装置使用这两个指示器将在远程存储器地址范围内的所有高速缓存行传送到远程存储器，然后由于系统维护或动态分区而动态地删除本地缓存资源。
-
公开(公告)号：US5860093A
公开(公告)日：1999-01-12
申请号：US785873
申请日：1997-01-21
CPC分类号： G06F12/0877 , G06F12/0851
摘要： Method and apparatus for reducing address/function transfer pins in a system where cache memories in a system controller are accessed by a number of instruction processors. The reduction of pins is obtained by using two data transfers. The increase in data addressing time, which would otherwise occur using two data transfers, is reduced to nearly the time of the data transfers themselves by responding to the first data transfer while the second data transfer is taking place.
摘要翻译： 用于减少系统控制器中的高速缓存存储器被多个指令处理器访问的系统中的地址/功能传输引脚的方法和装置。 通过使用两个数据传输来获得引脚的减少。 数据寻址时间的增加，否则将使用两个数据传输发生，在第二次数据传输发生时，通过响应第一次数据传输，自身数据传输的时间减少到几乎接近时间。
-
公开(公告)号：US06928517B1
公开(公告)日：2005-08-09
申请号：US09651597
申请日：2000-08-30
CPC分类号： G06F12/0811
摘要： A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from enhancing the response to SNOOP requests. To accomplish this, the system memory bus is provided separate and independent paths to the level two cache and tag memories. Therefore, SNOOP requests are permitted to directly access the tag memories without reference to the cache memory. Secondly, the SNOOP requests are given a higher priority than operations associated with local processor data requests. Though this may slow down the local processor, the remote processors have less wait time for SNOOP operations improving overall system performance.
摘要翻译： 一种用于提高采用多级高速缓冲存储器系统的数据处理系统的效率的方法和装置。 提高效率是由于增强了对SNOOP请求的响应。 为了实现这一点，系统存储器总线被提供到二级高速缓存和标签存储器的独立和独立的路径。 因此，SNOOP请求被允许直接访问标签存储器而不参考高速缓冲存储器。 其次，SNOOP请求的优先级高于与本地处理器数据请求相关的操作。 虽然这可能会减慢本地处理器的速度，但是远程处理器的SNOOP操作的等待时间较少，从而提高了系统的整体性能。
-
公开(公告)号：US06799249B1
公开(公告)日：2004-09-28
申请号：US09651598
申请日：2000-08-30
申请人： Donald C. Englin , Kelvin S. Vartti
发明人： Donald C. Englin , Kelvin S. Vartti
IPC分类号： G06F1200
CPC分类号： G06F12/0859
摘要： An apparatus for and method of queuing memory access requests resulting from level two cache memory misses. The requests are preferably queued separately by processor. To provide the most recent data to the system, write (i.e., input) requests are optimally given preference over read (i.e., output) requests for input/output processors. However, instruction processor program instruction fetches (i.e., read-only requests) are preferably given priority over operand transfers (i.e., read/write requests) to reduce instruction processor latency.
摘要翻译： 排队由二级高速缓存存储器未命中引起的存储器访问请求的装置和方法。 请求优选地由处理器排队。 为了向系统提供最新的数据，对输入/输出处理器的写入（即，输入）请求被优化地优先于读取（即输出）请求。 然而，指令处理器程序指令取出（即只读请求）优选地优先于操作数传送（即读/写请求）以减少指令处理器等待时间。
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.032 秒)
