利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

65 条记录 (耗时 0.026 秒)

    Cache flush system and method
    1.
    发明授权
    Cache flush system and method 失效
    缓存刷新系统和方法

    公开(公告)号：US06976128B1

    公开(公告)日：2005-12-13

    申请号：US10255420

    申请日：2002-09-26

    申请人： James A. Williams ,  Robert H. Andrighetti ,  Conrad S. Shimada ,  Donald C. Englin

    发明人： James A. Williams ,  Robert H. Andrighetti ,  Conrad S. Shimada ,  Donald C. Englin

    IPC分类号： G06F9/30 ,  G06F12/00 ,  G06F12/08 ,  G06F12/12

    CPC分类号： G06F9/30047 ,  G06F12/0804 ,  G06F12/127

    摘要： A system and method is provided to selectively flush data from cache memory to a main memory irrespective of the replacement algorithm that is used to manage the cache data. According to one aspect of the invention, novel “page flush” and “cache line flush” instructions are provided to flush a page and a cache line of memory data, respectively, from a cache to a main memory. In one embodiment, these instructions are included within the hardware instruction set of an Instruction Processor (IP). According to another aspect of the invention, flush operations are initiated using a background interface that interconnects the IP with its associated cache memory. A primary interface that also interconnects the IP to the cache memory is used to simultaneously issue higher-priority requests so that processor throughput is increased.

    摘要翻译： 提供了一种系统和方法，用于选择性地将数据从高速缓存存储器刷新到主存储器，而与用于管理高速缓存数据的替换算法无关。 根据本发明的一个方面，提供了新颖的“页面刷新”和“高速缓存行刷新”指令，用于将存储器数据的页面和高速缓存行分别从缓存刷新到主存储器。 在一个实施例中，这些指令被包括在指令处理器（IP）的硬件指令集中。 根据本发明的另一方面，使用将IP与其相关联的高速缓冲存储器互连的后台接口来启动刷新操作。 也将IP与高速缓冲存储器互连的主界面用于同时发出较高优先级的请求，从而提高处理器吞吐量。

    Cache apparatus and method for accesses lacking locality
    2.
    发明授权
    Cache apparatus and method for accesses lacking locality 有权
    缓存设备和访问方法缺乏本地化

    公开(公告)号：US07356650B1

    公开(公告)日：2008-04-08

    申请号：US11156225

    申请日：2005-06-17

    申请人： Donald C. Englin ,  James A. Williams

    发明人： Donald C. Englin ,  James A. Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0888 ,  G06F12/0811

    摘要： Systems and methods are provided for a data processing system and a cache arrangement. The data processing system includes at least one processor, a first-level cache, a second-level cache, and a memory arrangement. The first-level cache bypasses storing data for a memory request when a do-not-cache attribute is associated with the memory request. The second-level cache stores the data for the memory request. The second-level cache also bypasses updating of least-recently-used indicators of the second-level cache when the do-not-cache attribute is associated with the memory request.

    摘要翻译： 为数据处理系统和缓存装置提供了系统和方法。 数据处理系统包括至少一个处理器，第一级高速缓存，二级高速缓存和存储器布置。 当不高速缓存属性与存储器请求相关联时，第一级缓存绕过存储器请求的存储数据。 第二级缓存存储用于存储器请求的数据。 当不高速缓存属性与存储器请求相关联时，二级缓存也绕过二级缓存的最近最少使用的指示符的更新。

    System and method for maintaining memory coherency within a multi-processor data processing system
    3.
    发明授权
    System and method for maintaining memory coherency within a multi-processor data processing system 有权
    用于在多处理器数据处理系统内维持存储器一致性的系统和方法

    公开(公告)号：US07065614B1

    公开(公告)日：2006-06-20

    申请号：US10600880

    申请日：2003-06-20

    申请人： Kelvin S. Vartti ,  James A. Williams ,  Donald C. Englin

    发明人： Kelvin S. Vartti ,  James A. Williams ,  Donald C. Englin

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G06F12/0817

    摘要： The current invention provides a system and method for maintaining memory coherency within a multiprocessor environment that includes multiple requesters such as instruction processors coupled to a shared main memory. Within the system of the current invention, data may be provided from the shared memory to a requester for update purposes before all other read-only copies of this data stored elsewhere within the system have been invalidated. To ensure that this acceleration mechanism does not result in memory incoherency, an instruction is provided for inclusion within the instruction set of the processor. Execution of this instruction causes the executing processor to discontinue execution until all outstanding invalidation activities have completed for any data that has been retrieved and updated by the processor.

    摘要翻译： 本发明提供了一种用于在多处理器环境内维持存储器一致性的系统和方法，所述多处理器环境包括多个请求者，例如耦合到共享主存储器的指令处理器。 在本发明的系统内，在系统内其他地方存储的该数据的所有其它只读副本已被无效之前，可以从共享存储器向请求者提供数据用于更新目的。 为了确保这种加速机制不会导致内存不连续性，提供了用于包含在处理器的指令集内的指令。 该指令的执行将导致执行处理器停止执行，直到所有未完成的无效活动已经完成，处理器已检索和更新的任何数据。

    Data pre-fetch system and method for a cache memory
    4.
    发明授权
    Data pre-fetch system and method for a cache memory 失效
    缓存存储器的数据预取系统和方法

    公开(公告)号：US06993630B1

    公开(公告)日：2006-01-31

    申请号：US10255393

    申请日：2002-09-26

    申请人： James A. Williams ,  Robert H. Andrighetti ,  Conrad S. Shimada ,  Donald C. Englin ,  Kelvin S. Vartti

    发明人： James A. Williams ,  Robert H. Andrighetti ,  Conrad S. Shimada ,  Donald C. Englin ,  Kelvin S. Vartti

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0862

    摘要： A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache. Predetermined ones of the requests are provided to pre-fetch control logic, which determines whether the data signals are available within the cache. If not, the data signals are retrieved from another memory within the data processing system, and are stored to the cache. According to one aspect, the rate at which pre-fetch requests are generated may be programmably selected to match the rate at which the associated requests to access the data signals are provided to the cache. In another embodiment, pre-fetch control logic receives information to generate pre-fetch requests using a dedicated interface coupling the pre-fetch control logic to the IP.

    摘要翻译： 公开了一种用于预取数据信号的系统和方法。 根据本发明的一个方面，指令处理器（IP）产生访问高速缓存内的数据信号的请求。 将预定的请求提供给预取控制逻辑，其确定数据信号是否在高速缓存内可用。 如果不是，数据信号从数据处理系统中的另一个存储器检索，并被存储到高速缓存。 根据一个方面，可以可编程地选择生成预取请求的速率以匹配将相关联的数据信号请求提供给高速缓存的速率。 在另一个实施例中，预取控制逻辑接收信息以使用将预取控制逻辑耦合到IP的专用接口来生成预取请求。

    E. COLI PLASMID DNA PRODUCTION
    5.
    发明申请
    E. COLI PLASMID DNA PRODUCTION 有权
    大肠杆菌DNA生产

    公开(公告)号：US20100184157A1

    公开(公告)日：2010-07-22

    申请号：US12601504

    申请日：2008-05-22

    申请人： James A. Williams ,  Clague P. Hodgson ,  Aaron E. Carnes

    发明人： James A. Williams ,  Clague P. Hodgson ,  Aaron E. Carnes

    IPC分类号： C12N15/64 ,  C12N1/21

    CPC分类号： C12N15/64 ,  C12N1/06 ,  C12N15/1003 ,  C12N15/1017 ,  C12N15/73

    摘要： General methods and strains of bacteria are described, that dramatically simplify and streamline plasmid DNA production. In one preferred embodiment, endolysin mediated plasmid extraction combined with flocculation mediated removal of cell debris and host nucleic acids achieves increased yield and purity with simplified downstream purification and reduced waste streams, thus reducing production costs.

    摘要翻译： 描述了一般方法和细菌菌株，其显着简化和简化质粒DNA生产。 在一个优选的实施方案中，细胞内溶素介导的质粒提取结合絮凝介导的细胞碎片和宿主核酸的去除通过简化的下游纯化和减少的废物流实现了增加的产量和纯度，从而降低了生产成本。

    Mouth bite device
    9.
    发明授权
    Mouth bite device 失效
    嘴咬装置

    公开(公告)号：US5263976A

    公开(公告)日：1993-11-23

    申请号：US822886

    申请日：1992-01-21

    申请人： James A. Williams

    发明人： James A. Williams

    IPC分类号： A61J17/00

    CPC分类号： A61F5/566

    摘要： The mouth bite device includes a handle and a crossbar thereon to form a T-shaped device. The crossbar has resilient sections toward its ends. The device is sized so that the handle can manipulate the crossbar so that the crossbar enters across the mouth and the resilient sections respectively lie between the opposing molars of the user so that, as he bites down, he engages his molars on the resilient sections. This permits the user to clench his teeth without damage, thus relieving tension and releasing emotional energy.

    摘要翻译： 口咬装置包括手柄和横杆以形成T形装置。 横杆具有朝向其端部的弹性部分。 该装置的尺寸使得手柄能够操纵横杆，使得横杆进入口中，并且弹性部分分别位于使用者的相对的臼齿之间，使得当他咬下时，他将其臼齿接合在弹性部分上。 这样就可以让使用者咬紧牙齿而不受损伤，从而减轻紧张感并释放出情绪上的能量。