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    Software prefetch system and method for predetermining amount of streamed data
    1.
    发明授权
    Software prefetch system and method for predetermining amount of streamed data 失效
    软件预取系统和预测流数据量的方法

    公开(公告)号：US06574712B1

    公开(公告)日：2003-06-03

    申请号：US09550180

    申请日：2000-04-14

    申请人： James Allan Kahle ,  Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray ,  Edward John Silha ,  Joel M. Tendler

    发明人： James Allan Kahle ,  Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray ,  Edward John Silha ,  Joel M. Tendler

    IPC分类号： G06F1208

    CPC分类号： G06F9/383 ,  G06F9/30047 ,  G06F9/3802 ,  G06F12/0862 ,  G06F12/0897 ,  G06F2212/6028

    摘要： A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction is used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine. The instruction also limits the amount of data to be prefetched.

    摘要翻译： 数据处理系统包括具有第一级高速缓存和预取引擎的处理器。 耦合到处理器的是二级缓存和第三级缓存和系统存储器。 通过预取引擎对高速缓存行的预取执行到第一，第二和第三级高速缓存中的每一个。 从预取引擎到第二和第三级高速缓存的预取请求通过专用预取请求总线执行，该专用预取请求总线与将数据从各种高速缓存级别传送到处理器的总线系统分开。 软件指令用于通过覆盖硬件预取引擎的正常功能来加速预取过程。 该指令还限制了要预取的数据量。

    Cache prefetching of L2 and L3
    3.
    发明授权
    Cache prefetching of L2 and L3 失效
    缓存预取L2和L3

    公开(公告)号：US06446167B1

    公开(公告)日：2002-09-03

    申请号：US09435861

    申请日：1999-11-08

    申请人： Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray

    发明人： Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray

    IPC分类号： G06F938

    CPC分类号： G06F9/3802 ,  G06F12/0862 ,  G06F12/0897 ,  G06F2212/6026 ,  G06F2212/6028

    摘要： A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. The prefetch request may include a signal notifying the third level cache to also prefetch.

    摘要翻译： 数据处理系统包括具有第一级高速缓存和预取引擎的处理器。 耦合到处理器的是二级缓存和第三级缓存和系统存储器。 通过预取引擎对高速缓存行的预取执行到第一，第二和第三级高速缓存中的每一个。 从预取引擎到第二和第三级高速缓存的预取请求通过专用预取请求总线执行，该专用预取请求总线与将数据从各种高速缓存级别传送到处理器的总线系统分开。 预取请求可以包括通知第三级缓存也预取的信号。

    System and method for prefetching data using a hardware prefetch mechanism
    4.
    发明授权
    System and method for prefetching data using a hardware prefetch mechanism 失效
    使用硬件预取机制预取数据的系统和方法

    公开(公告)号：US06535962B1

    公开(公告)日：2003-03-18

    申请号：US09435860

    申请日：1999-11-08

    申请人： Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray

    发明人： Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray

    IPC分类号： G06F1200

    CPC分类号： G06F12/0862 ,  G06F12/0897 ,  G06F2212/6026 ,  G06F2212/6028

    摘要： A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.

    摘要翻译： 数据处理系统包括具有第一级高速缓存和预取引擎的处理器。 耦合到处理器的是二级缓存和第三级缓存和系统存储器。 通过预取引擎对高速缓存行的预取执行到第一，第二和第三级高速缓存中的每一个。 从预取引擎到第二和第三级高速缓存的预取请求通过专用预取请求总线执行，该专用预取请求总线与将数据从各种高速缓存级别传送到处理器的总线系统分开。

    System and method for selectively controlling fetching and prefetching of data to a processor
    6.
    发明授权
    System and method for selectively controlling fetching and prefetching of data to a processor 失效
    用于选择性地控制将数据提取和预取到处理器的系统和方法

    公开(公告)号：US6085291A

    公开(公告)日：2000-07-04

    申请号：US554180

    申请日：1995-11-06

    申请人： Dwain Alan Hicks ,  Michael John Mayfield ,  David Scott Ray ,  Shih-Hsiung Stephen Tung

    发明人： Dwain Alan Hicks ,  Michael John Mayfield ,  David Scott Ray ,  Shih-Hsiung Stephen Tung

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/00

    CPC分类号： G06F9/383 ,  G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6026

    摘要： Within a data processing system implementing primary and secondary caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. Prefetching may be performed on cache misses or hits. Cache misses on successive cache lines may allocate a stream of cache lines to the stream buffers. Control circuitry, coupled to a stream filter circuit, selectively controls fetching and prefetching of data from system memory to the primary and secondary caches associated with a processor and to a stream buffer circuit.

    摘要翻译： 在实现主和次高速缓存和流过滤器和缓冲器的数据处理系统中，缓存行的预取以渐进的方式执行。 在一种模式下，数据可能不被预取。 在第二模式中，预取两条高速缓存线，其中一行被预取到L1高速缓存中，并且下一行被预取到流缓冲器中。 在第三种模式下，一次预取多于两条的高速缓存行。 可以在高速缓存未命中或命中时执行预取。 连续缓存行上的缓存未命中可能会将流缓存行分配给流缓冲区。 耦合到流滤波器电路的控制电路选择性地控制数据从系统存储器到与处理器和流缓冲器电路相关联的主和次高速缓存的取样和预取。

    Method of load/store dependencies detection with dynamically changing address length
    9.
    发明授权
    Method of load/store dependencies detection with dynamically changing address length 失效
    使用动态变化的地址长度进行加载/存储依赖关系检测的方法

    公开(公告)号：US07464242B2

    公开(公告)日：2008-12-09

    申请号：US11050039

    申请日：2005-02-03

    申请人： Brian David Barrick ,  Dwain Alan Hicks ,  Takeki Osanai ,  David Scott Ray

    发明人： Brian David Barrick ,  Dwain Alan Hicks ,  Takeki Osanai ,  David Scott Ray

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0623 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0802

    摘要： A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline and the queues to avoid address conflicts. Overall, the present invention introduces a cache hit or cache miss input into the load/store dependency logic. If the incoming load operation is a cache hit, then the quadword boundary address value is used for detection. If the incoming load operation is a cache miss, then the cacheline boundary address value is used for detection. This invention enhances the performance of LHS and LHR operations in a memory system.

    摘要翻译： 提供了一种方法，装置和计算机程序产品，用于通过动态地改变地址宽度进行比较来检测存储器系统中的加载/存储相关性。 必须将进入的加载/存储操作与流水线和队列中的操作进行比较，以避免地址冲突。 总的来说，本发明将缓存命中或高速缓存未命中输入引入到加载/存储依赖逻辑中。 如果进入加载操作是缓存命中，则使用四字边界地址值进行检测。 如果进入加载操作是高速缓存未命中，则使用高速缓存行边界地址值进行检测。 本发明增强了存储系统中LHS和LHR操作的性能。

    Method and systems for executing load instructions that achieve sequential load consistency
    10.
    发明授权
    Method and systems for executing load instructions that achieve sequential load consistency 失效
    执行负载指令的方法和系统，以实现连续的负载一致性

    公开(公告)号：US07376816B2

    公开(公告)日：2008-05-20

    申请号：US10988310

    申请日：2004-11-12

    申请人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    发明人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/383 ,  G06F12/0855

    摘要： A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

    摘要翻译： 公开了一种用于执行加载指令的方法。 加载指令的地址信息用于生成所需数据的地址，该地址用于搜索所需数据的高速缓冲存储器。 如果在高速缓冲存储器中找到所需的数据，则产生高速缓存命中信号。 地址的至少一部分用于在队列中搜索指定相同地址的先前加载指令。 如果找到指定相同地址的先前加载指令，则忽略缓存命中信号，并将加载指令存储在队列中。 还描述了加载/存储单元和实现该方法的处理器。