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    Configurable integrated circuit capacitor array using via mask layers
    2.
    发明授权
    Configurable integrated circuit capacitor array using via mask layers 有权
    可配置的集成电路电容阵列使用通孔掩模层

    公开(公告)号：US07335966B2

    公开(公告)日：2008-02-26

    申请号：US10906527

    申请日：2005-02-23

    申请人： David Ihme ,  James C. Kemerling ,  William D. Cox

    发明人： David Ihme ,  James C. Kemerling ,  William D. Cox

    IPC分类号： H01L29/00

    CPC分类号： H01G4/385 ,  H01L27/0805 ,  H01L2924/14 ,  H01L2924/00

    摘要： A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.

    摘要翻译： 具有多个层的半导体器件和包括多个单独的电容器的电容器阵列。 半导体器件中的多个层中的至少一个可以是被配置为确定电容器阵列中的多个单独电容器的连接和电容的通孔层。 半导体器件可以包括设置在器件内的金属结构，以为电容器阵列中的多个独立电容器中的至少一个提供电磁屏蔽。

    VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE
    3.
    发明申请
    VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE 有权
    通过半导体器件中模拟电路自定义的可配置架构

    公开(公告)号：US20090032968A1

    公开(公告)日：2009-02-05

    申请号：US12246802

    申请日：2008-10-07

    申请人： James C. Kemerling ,  David Ihme ,  William D. Cox

    发明人： James C. Kemerling ,  David Ihme ,  William D. Cox

    IPC分类号： H01L23/522

    CPC分类号： H03K19/17736 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17748 ,  H03K19/17796 ,  H01L2924/00

    摘要： A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

    摘要翻译： 具有多个层的半导体器件和布置在瓦片中的多个电路元件。 半导体器件中的多个层中的至少一个可以是经配置以确定多个电路元件的连接的通孔层。 半导体器件可以包括具有设置成互连多个电路元件的多个金属层的互连被子。 多个电路元件可以是模拟电路元件和/或数字电路元件。 瓦片可以是形成混合信号结构阵列的模拟瓦片和数字瓦片。

    VIA configurable architecture for customization of analog circuitry in a semiconductor device
    4.
    发明授权
    VIA configurable architecture for customization of analog circuitry in a semiconductor device 有权
    VIA可配置架构，用于定制半导体器件中的模拟电路

    公开(公告)号：US07449371B2

    公开(公告)日：2008-11-11

    申请号：US10907456

    申请日：2005-04-01

    申请人： James C. Kemerling ,  David Ihme ,  William D Cox

    发明人： James C. Kemerling ,  David Ihme ,  William D Cox

    IPC分类号： H01L21/82

    CPC分类号： H03K19/17736 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17748 ,  H03K19/17796 ,  H01L2924/00

    摘要： A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

    摘要翻译： 具有多个层的半导体器件和布置在瓦片中的多个电路元件。 半导体器件中的多个层中的至少一个可以是被配置为确定多个电路元件的连接的通孔层。 半导体器件可以包括具有设置成互连多个电路元件的多个金属层的互连被子。 多个电路元件可以是模拟电路元件和/或数字电路元件。 瓦片可以是形成混合信号结构阵列的模拟瓦片和数字瓦片。

    Via configurable architecture for customization of analog circuitry in a semiconductor device
    5.
    发明授权
    Via configurable architecture for customization of analog circuitry in a semiconductor device 有权
    通过可配置的架构，用于定制半导体器件中的模拟电路

    公开(公告)号：US07972907B2

    公开(公告)日：2011-07-05

    申请号：US12268919

    申请日：2008-11-11

    申请人： James C. Kemerling ,  David Ihme ,  William D. Cox

    发明人： James C. Kemerling ,  David Ihme ,  William D. Cox

    IPC分类号： H01L21/82

    CPC分类号： H03K19/17736 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17748 ,  H03K19/17796 ,  H01L2924/00

    摘要： A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

    摘要翻译： 具有多个层的半导体器件和布置在瓦片中的多个电路元件。 半导体器件中的多个层中的至少一个可以是经配置以确定多个电路元件的连接的通孔层。 半导体器件可以包括具有设置成互连多个电路元件的多个金属层的互连被子。 多个电路元件可以是模拟电路元件和/或数字电路元件。 瓦片可以是形成混合信号结构阵列的模拟瓦片和数字瓦片。

    Via configurable architecture for customization of analog circuitry in a semiconductor device
    6.
    发明授权
    Via configurable architecture for customization of analog circuitry in a semiconductor device 有权
    通过可配置的架构，用于定制半导体器件中的模拟电路

    公开(公告)号：US07626272B2

    公开(公告)日：2009-12-01

    申请号：US12246802

    申请日：2008-10-07

    申请人： James C. Kemerling ,  David Ihme ,  William D. Cox

    发明人： James C. Kemerling ,  David Ihme ,  William D. Cox

    IPC分类号： H01L23/12 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H03K19/17736 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17748 ,  H03K19/17796 ,  H01L2924/00

    摘要： A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

    摘要翻译： 具有多个层的半导体器件和布置在瓦片中的多个电路元件。 半导体器件中的多个层中的至少一个可以是经配置以确定多个电路元件的连接的通孔层。 半导体器件可以包括具有设置成互连多个电路元件的多个金属层的互连被子。 多个电路元件可以是模拟电路元件和/或数字电路元件。 瓦片可以是形成混合信号结构阵列的模拟瓦片和数字瓦片。

    Configurable integrated circuit capacitor array using via mask layers
    7.
    发明授权
    Configurable integrated circuit capacitor array using via mask layers 有权
    可配置的集成电路电容阵列使用通孔掩模层

    公开(公告)号：US07595229B2

    公开(公告)日：2009-09-29

    申请号：US11965069

    申请日：2007-12-27

    申请人： David Ihme ,  James C. Kemerling ,  William D. Cox

    发明人： David Ihme ,  James C. Kemerling ,  William D. Cox

    IPC分类号： H01L21/82

    CPC分类号： H01G4/385 ,  H01L27/0805 ,  H01L2924/14 ,  H01L2924/00

    摘要： A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.

    摘要翻译： 具有多个层的半导体器件和包括多个单独的电容器的电容器阵列。 半导体器件中的多个层中的至少一个可以是被配置为确定电容器阵列中的多个单独电容器的连接和电容的通孔层。 半导体器件可以包括设置在器件内的金属结构，以为电容器阵列中的多个独立电容器中的至少一个提供电磁屏蔽。

    Configurable Integrated Circuit Capacitor Array Using Via Mask Layers
    8.
    发明申请
    Configurable Integrated Circuit Capacitor Array Using Via Mask Layers 有权
    可配置的集成电路电容阵列使用通过掩模层

    公开(公告)号：US20080108201A1

    公开(公告)日：2008-05-08

    申请号：US11965069

    申请日：2007-12-27

    申请人： David Ihme ,  James Kemerling ,  William Cox

    发明人： David Ihme ,  James Kemerling ,  William Cox

    IPC分类号： H01L21/20

    CPC分类号： H01G4/385 ,  H01L27/0805 ,  H01L2924/14 ,  H01L2924/00

    摘要： A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.

    摘要翻译： 具有多个层的半导体器件和包括多个单独的电容器的电容器阵列。 半导体器件中的多个层中的至少一个可以是被配置为确定电容器阵列中的多个单独电容器的连接和电容的通孔层。 半导体器件可以包括设置在器件内的金属结构，以为电容器阵列中的多个独立电容器中的至少一个提供电磁屏蔽。

    CONFIGURABLE INTEGRATED CIRCUIT CAPACITOR ARRAY USING VIA MASK LAYERS
    9.
    发明申请
    CONFIGURABLE INTEGRATED CIRCUIT CAPACITOR ARRAY USING VIA MASK LAYERS 有权
    可配置的集成电路电容器阵列使用掩模层

    公开(公告)号：US20050189614A1

    公开(公告)日：2005-09-01

    申请号：US10906527

    申请日：2005-02-23

    申请人： David Ihme ,  James Kemerling ,  William Cox

    发明人： David Ihme ,  James Kemerling ,  William Cox

    IPC分类号： H01G4/30 ,  H01G4/38 ,  H01L23/522 ,  H01L27/08 ,  H01L29/00

    CPC分类号： H01G4/385 ,  H01L27/0805 ,  H01L2924/14 ,  H01L2924/00

    摘要： A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.

    摘要翻译： 具有多个层的半导体器件和包括多个单独的电容器的电容器阵列。 半导体器件中的多个层中的至少一个可以是被配置为确定电容器阵列中的多个单独电容器的连接和电容的通孔层。 半导体器件可以包括设置在器件内的金属结构，以为电容器阵列中的多个独立电容器中的至少一个提供电磁屏蔽。

    VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE
    10.
    发明申请
    VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE 有权
    通过半导体器件中模拟电路自定义的可配置架构

    公开(公告)号：US20050224982A1

    公开(公告)日：2005-10-13

    申请号：US10907456

    申请日：2005-04-01

    申请人： James Kemerling ,  David Ihme ,  William Cox

    发明人： James Kemerling ,  David Ihme ,  William Cox

    IPC分类号： H01L27/118 ,  H03K19/177 ,  H01L23/52 ,  H01L21/4763

    CPC分类号： H03K19/17736 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17748 ,  H03K19/17796 ,  H01L2924/00

    摘要： A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

    摘要翻译： 具有多个层的半导体器件和布置在瓦片中的多个电路元件。 半导体器件中的多个层中的至少一个可以是被配置为确定多个电路元件的连接的通孔层。 半导体器件可以包括具有设置成互连多个电路元件的多个金属层的互连被子。 多个电路元件可以是模拟电路元件和/或数字电路元件。 瓦片可以是形成混合信号结构阵列的模拟瓦片和数字瓦片。