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    Decoupling dynamic program analysis from execution across heterogeneous systems
    1.
    发明授权
    Decoupling dynamic program analysis from execution across heterogeneous systems 有权
    将异步系统中的动态程序分析与执行分解

    公开(公告)号：US08352240B2

    公开(公告)日：2013-01-08

    申请号：US12239648

    申请日：2008-09-26

    Applicant: James Chow ,  Tal Garfinkel ,  Peter M. Chen

    Inventor： James Chow ,  Tal Garfinkel ,  Peter M. Chen

    IPC: G06F9/45

    CPC classification number: G06F11/3612 ,  G06F9/45558 ,  G06F11/3636 ,  G06F2009/45591

    Abstract: Dynamic program analysis is decoupled from execution in virtual computer environments so that program analysis can be performed on a running computer program without affecting or perturbing the workload of the system on which the program is executing. Decoupled dynamic program analysis is enabled by separating execution and analysis into two tasks: (1) recording, where system execution is recorded with minimal interference, and (2) analysis, where the execution is replayed and analyzed. Recording and analysis are carried out on heterogeneous systems so that they can be separately optimized.

    Abstract translation: 动态程序分析与虚拟计算机环境中的执行脱钩，以便可以在运行的计算机程序上执行程序分析，而不会影响或扰乱程序正在执行的系统的工作负载。 通过将执行和分析分为两个任务来实现解耦动态程序分析：（1）录制，其中以最小的干扰记录系统执行，以及（2）分析，执行被重放和分析。 在异构系统上进行记录和分析，以便可以单独进行优化。

    Versatile RSDS-LVDS-miniLVDS-BLVDS differential signal interface circuit
    5.
    发明授权
    Versatile RSDS-LVDS-miniLVDS-BLVDS differential signal interface circuit 有权
    通用RSDS-LVDS-miniLVDS-BLVDS差分信号接口电路

    公开(公告)号：US06992508B2

    公开(公告)日：2006-01-31

    申请号：US10877543

    申请日：2004-06-25

    Applicant: James Chow

    Inventor： James Chow

    IPC: H03K19/094

    CPC classification number: H03K19/018585 ,  H04L25/0272 ,  H04L25/028 ,  H04M3/42017

    Abstract: An electronic circuit includes a selectively configurable differential signal interface and a selection control input for selecting one of a plurality of standard differential signal interfaces for configuration of the differential signal interface. The selection control input selects one of the following plurality of standard differential signal interfaces: reduced swing differential signaling (RSDS), low voltage differential signaling (LVDS), mini low voltage differential signaling (mini-LVDS), and bussed low voltage differential signaling (BLVDS), for configuration of the differential signal interface. The electronic circuit may also include a plurality of selectable voltage sources (611, 612, 613) and a plurality of selectable current sources (614, 615, 616, 617), for selecting, in response to an input signal at the selection control input, at least one of an operating D.C. voltage, a standard differential signal voltage, and a standard differential signal current for the differential signal interface.

    Abstract translation: 电子电路包括可选择地配置的差分信号接口和选择控制输入，用于选择多个标准差分信号接口中的一个以配置差分信号接口。 选择控制输入选择以下多个标准差分信号接口之一：减速摆幅差分信号（RSDS），低电压差分信号（LVDS），迷你低电压差分信号（mini-LVDS）和总线低电压差分信号（ BLVDS），用于配置差分信号接口。 电子电路还可以包括多个可选择的电压源（611,612,613）和多个可选择的电流源（614,615,616,617），用于响应于选择控制输入端处的输入信号而选择 ，用于差分信号接口的操作DC电压，标准差分信号电压和标准差分信号电流中的至少一个。

    Precision closed loop delay line for wide frequency data recovery
    6.
    发明申请
    Precision closed loop delay line for wide frequency data recovery 有权
    精密闭环延迟线用于宽频数据恢复

    公开(公告)号：US20050017774A1

    公开(公告)日：2005-01-27

    申请号：US10921242

    申请日：2004-08-18

    Applicant: James Chow ,  Kenny Wen

    Inventor： James Chow ,  Kenny Wen

    IPC: H03H7/30 ,  H03L7/07 ,  H03L7/081 ,  H03B1/00

    CPC classification number: H03L7/0805 ,  H03L7/07 ,  H03L7/0812

    Abstract: A closed loop delay line system (700) includes a phase lock loop that provides a phase lock output signal (715). A delay line (702) includes a clock input, a delay line output, and a delay line bias input. A bias signal provided to the delay line bias input (727) adjusts the speed of the delay line (702). A phase detector (720) compares phase between a first timing signal input (704) and the delay line output (706). A bias adjust circuit (726) mixes the phase compare output signal (725) and the phase lock output signal (715) to provide a combination bias signal (727) to the delay line (702). Additionally, the relative timing position of strobe outputs (734) from the delay line (702) can be individually adjusted.

    Abstract translation: 闭环延迟线系统（700）包括提供锁相输出信号（715）的锁相环。 延迟线（702）包括时钟输入，延迟线输出和延迟线偏置输入。 提供给延迟线偏置输入（727）的偏置信号调整延迟线（702）的速度。 相位检测器（720）比较第一定时信号输入（704）和延迟线输出（706）之间的相位。 偏置调整电路（726）将相位比较输出信号（725）和锁相输出信号（715）混合，以向延迟线（702）提供组合偏置信号（727）。 此外，可以单独调整来自延迟线（702）的选通输出（734）的相对定时位置。

    Accelerating replayed program execution to support decoupled program analysis
    8.
    发明授权
    Accelerating replayed program execution to support decoupled program analysis 有权
    加速重播的程序执行，以支持解耦程序分析

    公开(公告)号：US08719800B2

    公开(公告)日：2014-05-06

    申请号：US12239691

    申请日：2008-09-26

    Applicant: James Chow ,  Tal Garfinkel ,  Peter M. Chen

    Inventor： James Chow ,  Tal Garfinkel ,  Peter M. Chen

    IPC: G06F9/44

    CPC classification number: G06F11/3612 ,  G06F9/45558 ,  G06F11/3636 ,  G06F2009/45591

    Abstract: A virtual machine system decouples dynamic program analysis from program execution. Program analysis is decoupled from program execution through the use of a virtual machine to record program execution and an analysis platform to replay and analyze the program execution. Optimization techniques are applied to prevent the analysis platform from falling too far behind the program execution platform during replay.

    Abstract translation: 虚拟机系统将动态程序分析与程序执行分离。 程序分析通过使用虚拟机记录程序执行和分析平台来重新分析程序执行与程序执行脱钩。 应用优化技术来防止分析平台在重放期间落后于程序执行平台。

    Method and system for recording a selected computer process for subsequent replay
    9.
    发明授权
    Method and system for recording a selected computer process for subsequent replay 有权
    用于记录所选计算机进程以用于随后重放的方法和系统

    公开(公告)号：US08656222B2

    公开(公告)日：2014-02-18

    申请号：US12512288

    申请日：2009-07-30

    Applicant: James Chow ,  Tal Garfinkel ,  Dominic Lucchetti

    Inventor： James Chow ,  Tal Garfinkel ,  Dominic Lucchetti

    IPC: G06F11/00

    CPC classification number: G06F11/3476 ,  G06F11/3495 ,  G06F11/3636

    Abstract: The execution behavior of a selected application is recorded for subsequent replay. During recording, only those portions of memory that are accessed by the selected application are stored. As a result, the amount of data that is stored during the recording session is reduced and data that is not necessary for replaying the selected application, which may include possible sensitive and personal information, are not stored.

    Abstract translation: 记录所选应用程序的执行行为，以便后续重播。 在记录期间，仅存储由所选择的应用访问的存储器部分。 结果，减少了在记录会话期间存储的数据量，并且不存储可能包括可能的敏感和个人信息的重放所选择的应用所需的数据。

    PROSTHETIC FEMORAL STEM FOR USE IN HIGH OFFSET HIP REPLACEMENT
    10.
    发明申请
    PROSTHETIC FEMORAL STEM FOR USE IN HIGH OFFSET HIP REPLACEMENT 审中-公开
    在高位置髋关节置换中使用的先天性股骨干

    公开(公告)号：US20120065737A1

    公开(公告)日：2012-03-15

    申请号：US13227291

    申请日：2011-09-07

    Applicant: James Chow

    Inventor： James Chow

    IPC: A61F2/32

    CPC classification number: A61F2/3662 ,  A61F2/367 ,  A61F2002/30604

    Abstract: A total hip femoral prosthesis provides high lateral offset with a construct including a conventional length neck. The neck is shifted medially to position the head center in a high offset location. The proximal medial portion of the stem is augmented to provide adequate support to the medialized neck. Modular components are disclosed. Methods of using the prosthesis in total hip arthroplasty are described.

    Abstract translation: 全髋关节股骨假体提供具有常规长度颈部的构造的高侧向偏移。 颈部中间移位，将头部中心定位在高偏移位置。 杆的近端内侧部分被增大以向内侧化的颈部提供足够的支撑。 公开了模块化组件。 描述了在全髋关节置换术中使用假体的方法。

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