DECOUPLING DYNAMIC PROGRAM ANALYSIS FROM EXECUTION IN VIRTUAL ENVIRONMENTS
    1.
    发明申请
    DECOUPLING DYNAMIC PROGRAM ANALYSIS FROM EXECUTION IN VIRTUAL ENVIRONMENTS 有权
    解除虚拟环境中的执行动态程序分析

    公开(公告)号:US20090320009A1

    公开(公告)日:2009-12-24

    申请号:US12239590

    申请日:2008-09-26

    Abstract: Dynamic program analysis is decoupled from execution in virtual computer environments so that program analysis can be performed on a running computer program without affecting or perturbing the workload of the system on which the program is executing. Decoupled dynamic program analysis is enabled by separating execution and analysis into two tasks: (1) recording, where system execution is recorded with minimal interference, and (2) analysis, where the execution is replayed and analyzed.

    Abstract translation: 动态程序分析与虚拟计算机环境中的执行脱钩,以便可以在运行的计算机程序上执行程序分析,而不会影响或扰乱程序正在执行的系统的工作负载。 通过将执行和分析分为两个任务来实现解耦动态程序分析:(1)录制,其中以最小的干扰记录系统执行,以及(2)分析,执行被重放和分析。

    Accelerating replayed program execution to support decoupled program analysis
    2.
    发明授权
    Accelerating replayed program execution to support decoupled program analysis 有权
    加速重播的程序执行,以支持解耦程序分析

    公开(公告)号:US08719800B2

    公开(公告)日:2014-05-06

    申请号:US12239691

    申请日:2008-09-26

    Abstract: A virtual machine system decouples dynamic program analysis from program execution. Program analysis is decoupled from program execution through the use of a virtual machine to record program execution and an analysis platform to replay and analyze the program execution. Optimization techniques are applied to prevent the analysis platform from falling too far behind the program execution platform during replay.

    Abstract translation: 虚拟机系统将动态程序分析与程序执行分离。 程序分析通过使用虚拟机记录程序执行和分析平台来重新分析程序执行与程序执行脱钩。 应用优化技术来防止分析平台在重放期间落后于程序执行平台。

    Method and system for recording a selected computer process for subsequent replay
    3.
    发明授权
    Method and system for recording a selected computer process for subsequent replay 有权
    用于记录所选计算机进程以用于随后重放的方法和系统

    公开(公告)号:US08656222B2

    公开(公告)日:2014-02-18

    申请号:US12512288

    申请日:2009-07-30

    CPC classification number: G06F11/3476 G06F11/3495 G06F11/3636

    Abstract: The execution behavior of a selected application is recorded for subsequent replay. During recording, only those portions of memory that are accessed by the selected application are stored. As a result, the amount of data that is stored during the recording session is reduced and data that is not necessary for replaying the selected application, which may include possible sensitive and personal information, are not stored.

    Abstract translation: 记录所选应用程序的执行行为,以便后续重播。 在记录期间,仅存储由所选择的应用访问的存储器部分。 结果,减少了在记录会话期间存储的数据量,并且不存储可能包括可能的敏感和个人信息的重放所选择的应用所需的数据。

    PROSTHETIC FEMORAL STEM FOR USE IN HIGH OFFSET HIP REPLACEMENT
    4.
    发明申请
    PROSTHETIC FEMORAL STEM FOR USE IN HIGH OFFSET HIP REPLACEMENT 审中-公开
    在高位置髋关节置换中使用的先天性股骨干

    公开(公告)号:US20120065737A1

    公开(公告)日:2012-03-15

    申请号:US13227291

    申请日:2011-09-07

    Applicant: James Chow

    Inventor: James Chow

    CPC classification number: A61F2/3662 A61F2/367 A61F2002/30604

    Abstract: A total hip femoral prosthesis provides high lateral offset with a construct including a conventional length neck. The neck is shifted medially to position the head center in a high offset location. The proximal medial portion of the stem is augmented to provide adequate support to the medialized neck. Modular components are disclosed. Methods of using the prosthesis in total hip arthroplasty are described.

    Abstract translation: 全髋关节股骨假体提供具有常规长度颈部的构造的高侧向偏移。 颈部中间移位,将头部中心定位在高偏移位置。 杆的近端内侧部分被增大以向内侧化的颈部提供足够的支撑。 公开了模块化组件。 描述了在全髋关节置换术中使用假体的方法。

    METHOD AND SYSTEM FOR RECORDING A SELECTED COMPUTER PROCESS FOR SUBSEQUENT REPLAY
    5.
    发明申请
    METHOD AND SYSTEM FOR RECORDING A SELECTED COMPUTER PROCESS FOR SUBSEQUENT REPLAY 有权
    用于记录用于后续重现的所选计算机过程的方法和系统

    公开(公告)号:US20110029821A1

    公开(公告)日:2011-02-03

    申请号:US12512288

    申请日:2009-07-30

    CPC classification number: G06F11/3476 G06F11/3495 G06F11/3636

    Abstract: The execution behavior of a selected application is recorded for subsequent replay. During recording, only those portions of memory that are accessed by the selected application are stored. As a result, the amount of data that is stored during the recording session is reduced and data that is not necessary for replaying the selected application, which may include possible sensitive and personal information, are not stored.

    Abstract translation: 记录所选应用程序的执行行为,以便后续重播。 在记录期间,仅存储由所选择的应用访问的存储器部分。 结果,减少了在记录会话期间存储的数据量,并且不存储可能包括可能的敏感和个人信息的重放所选择的应用所需的数据。

    Low Power and Low Noise Differential Input Circuit
    7.
    发明申请
    Low Power and Low Noise Differential Input Circuit 审中-公开
    低功耗和低噪声差分输入电路

    公开(公告)号:US20080303545A1

    公开(公告)日:2008-12-11

    申请号:US11758665

    申请日:2007-06-05

    Applicant: James Chow

    Inventor: James Chow

    CPC classification number: H03K3/356139

    Abstract: A differential input circuit with lower power consumption and noise is disclosed. Rather than completely discharging output nodes differential circuits, the present invention equalizes the output nodes to conserver power and to reduce noise. Specifically, an equalization circuit is coupled between the output nodes of the low power and low noise differential input circuit.

    Abstract translation: 公开了具有较低功耗和噪声的差分输入电路。 本发明不是完全放电输出节点差分电路,而是将输出节点均衡以节省功率并降低噪声。 具体地,均衡电路耦合在低功率和低噪声差分输入电路的输出节点之间。

    Video analog-to-digital converter
    9.
    发明授权
    Video analog-to-digital converter 有权
    视频模数转换器

    公开(公告)号:US06490005B1

    公开(公告)日:2002-12-03

    申请号:US09607493

    申请日:2000-06-30

    Abstract: An analog-to-digital converter (ADC) (112) for sampling high speed video signals includes Pre-amplifiers (502, 504, 506) electrically coupled to Post-amplifiers (508, 510, 512) that are electrically coupled to output latches (514, 517, 519, 521, 523, 525, and 527). A sampling clock signal (116) clocks the output latches (514, 517, 519, 521, 523, 525, and 527) to sample an input analog electronic signal to provide a digital representation thereof. The ADC (112) includes an auto-zeroing function to cancel bias voltages at the Post-amplifiers (508, 510, 512) during a video signal horizontal blanking time period. The ADC (112) includes a bit dithering function by alternating sets of reference voltages into the Pre-amplifiers (502, 504, 506) increasing bit resolution. The ADC (112) includes wired interconnect interpolation between the Pre-amplifiers (502, 504, 506) and Post-amplifiers (508, 510, 512) and between the Post-amplifiers (508, 510, 512) and the output latches (514, 517, 519, 521, 523, 525, and 527).

    Abstract translation: 用于采样高速视频信号的模数转换器(ADC)(112)包括电耦合到后放大器(508,510,512)的前置放大器(502,504,506),后置放大器电耦合到输出锁存器 (514,517,519,521,523,525和527)。 采样时钟信号(116)对输出锁存器(514,517,519,521,523,525和527)进行时钟以采样输入的模拟电子信号以提供其数字表示。 ADC(112)包括在视频信号水平消隐时间段期间消除后置放大器(508,510,512)处的偏置电压的自动归零功能。 ADC(112)通过将增加比特分辨率的参考电压组交替到前置放大器(502,504,506)中而包括位抖动功能。 ADC(112)包括预放大器(502,504,506)和后置放大器(508,510,512)之间以及后置放大器(508,510,512)和输出锁存器 514,571,519,521,523,525和527)。

    Decoupling dynamic program analysis from execution across heterogeneous systems
    10.
    发明授权
    Decoupling dynamic program analysis from execution across heterogeneous systems 有权
    将异步系统中的动态程序分析与执行分解

    公开(公告)号:US08352240B2

    公开(公告)日:2013-01-08

    申请号:US12239648

    申请日:2008-09-26

    Abstract: Dynamic program analysis is decoupled from execution in virtual computer environments so that program analysis can be performed on a running computer program without affecting or perturbing the workload of the system on which the program is executing. Decoupled dynamic program analysis is enabled by separating execution and analysis into two tasks: (1) recording, where system execution is recorded with minimal interference, and (2) analysis, where the execution is replayed and analyzed. Recording and analysis are carried out on heterogeneous systems so that they can be separately optimized.

    Abstract translation: 动态程序分析与虚拟计算机环境中的执行脱钩,以便可以在运行的计算机程序上执行程序分析,而不会影响或扰乱程序正在执行的系统的工作负载。 通过将执行和分析分为两个任务来实现解耦动态程序分析:(1)录制,其中以最小的干扰记录系统执行,以及(2)分析,执行被重放和分析。 在异构系统上进行记录和分析,以便可以单独进行优化。

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