公开(公告)号：US07760843B2

公开(公告)日：2010-07-20

申请号：US12187517

申请日：2008-08-07

Applicant: David William Boerstler ,  Eric John Lukes ,  Hiroki Kihara ,  James David Strom

Inventor： David William Boerstler ,  Eric John Lukes ,  Hiroki Kihara ,  James David Strom

IPC: H03K21/00

CPC classification number: H03K21/406 ,  G06F7/58

Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.

Abstract translation: 本发明提供一种自校正状态电路。 第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。 第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。 第一校正电路耦合到第二触发器并且被配置为产生校正输出。 第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

公开(公告)号：US20080208541A1

公开(公告)日：2008-08-28

申请号：US11870159

申请日：2007-10-10

Applicant: Michael David Cesky ,  James David Strom

Inventor： Michael David Cesky ,  James David Strom

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  H03L7/18 ,  H03L7/1974

Abstract: A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL, and a design structure on which the subject circuit resides is provided. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.

Abstract translation: 一种方法和增强的锁相环（PLL）电路能够有效地测试PLL，并且提供主题电路所在的设计结构。 相位频率检测器产生差分信号，接收PLL电路的输出信号的参考信号和反馈信号。 电荷泵耦合到接收差分信号的相位频率检测器。 电荷泵将负电荷或正电荷脉冲施加到低通滤波器，产生施加到压控振荡器的调谐电压输入。 第一分频器耦合到压控振荡器接收并分频VCO输出信号，提供PLL电路的输出信号。 第二分频器接收PLL电路的输出信号，并将反馈信号提供给相位频率检测器。 PLL电路的输出信号应用于时钟分配。

公开(公告)号：US06239665B1

公开(公告)日：2001-05-29

申请号：US09432673

申请日：1999-11-02

Applicant: James David Strom

Inventor： James David Strom

IPC: H03B508

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1253 ,  H03B5/1265 ,  H03J2200/10

Abstract: A method and apparatus are provided for switching in metal insulator metal (MIM) capacitors and field effect transistor (FET) tuning capacitors for oscillator circuits. Apparatus for switching in metal-insulator-metal (MIM) capacitors and field effect transistor (FET) tuning capacitors for oscillator circuits includes a first differential oscillator node and a second differential oscillator node. A plurality of metal-insulator-metal (MIM) capacitors are connected to the first differential oscillator nodes and a plurality of metal-insulator-metal (MIM) capacitors are connected to the second differential oscillator nodes. A respective switching transistor is connected in series with an associated one of the metal-insulator-metal (MIM) capacitors. Each switching transistor receives a decoding input and is arranged for providing an open or a ground connection for the associated one of the metal-insulator-metal (MIM) capacitors. A first field effect transistor (FET) tuning capacitor has a gate connected to the first differential oscillator node. A second field effect transistor (FET) tuning capacitor has a gate connected to the second differential oscillator node. Each of the first field effect transistor (FET) tuning capacitor and the second field effect transistor (FET) tuning capacitor having a source and a drain connected together and a control voltage applied to the connected source and drain for varying tuning capacitance.

Abstract translation: 提供了用于切换用于振荡器电路的金属绝缘体金属（MIM）电容器和场效应晶体管（FET）调谐电容器的方法和装置。 用于切换用于振荡器电路的金属 - 绝缘体金属（MIM）电容器和场效应晶体管（FET）调谐电容器的装置包括第一差分振荡器节点和第二差分振荡器节点。 多个金属绝缘体金属（MIM）电容器连接到第一差分振荡器节点，并且多个金属 - 绝缘体金属（MIM）电容器连接到第二差分振荡器节点。 相应的开关晶体管与金属 - 绝缘体 - 金属（MIM）电容器中的相关联的一个串联连接。 每个开关晶体管接收解码输入，并且被布置成为金属 - 绝缘体 - 金属（MIM）电容器中相关联的一个提供开路或接地连接。 第一场效应晶体管（FET）调谐电容器具有连接到第一差分振荡器节点的栅极。 第二场效应晶体管（FET）调谐电容器具有连接到第二差分振荡器节点的栅极。 第一场效应晶体管（FET）调谐电容器和具有连接在一起的源极和漏极的第二场效应晶体管（FET）调谐电容器以及施加到所连接的源极和漏极的控制电压用于改变调谐电容。

公开(公告)号：US5903195A

公开(公告)日：1999-05-11

申请号：US16848

申请日：1998-01-30

Applicant: Eric John Lukes ,  James David Strom ,  Dana Marie Woeste

Inventor： Eric John Lukes ,  James David Strom ,  Dana Marie Woeste

IPC: H03L7/095 ,  H03L7/099 ,  H03L7/10 ,  H03L7/12

CPC classification number: H03L7/095 ,  H03L7/0995 ,  H03L7/10 ,  Y10S331/02

Abstract: An improved phase locked loop (PLL) circuit is provided for use in microprocessor clock generation. A ring oscillator provides an output frequency signal. A voltage to current converter converts differential control voltages to a variable reference current applied to the ring oscillator. A range control reference current generator applies a range control reference current to the ring oscillator. A range control operatively controls the range control reference current generator to sequentially change the range control reference current applied to the ring oscillator. A lock detector coupled to the range control compares the output frequency signal and a reference frequency signal and responsive to the compares signals applies a locked signal to the range control. Responsive to an applied locked signal, the range control stops changing ranges. The phase locked loop (PLL) circuit automatically sweeps through multiple frequency subranges responsive to the range control. A control signal is applied to the voltage to current converter for selectively controlling an operational mode of the voltage to current converter from a squelched operational mode to an unsquelched operational mode after a set time period. This control signal also is applied to the range control, so that the range control stops changing ranges.

Abstract translation: 提供改进的锁相环（PLL）电路用于微处理器时钟产生。 环形振荡器提供输出频率信号。 电压 - 电流转换器将差分控制电压转换为施加到环形振荡器的可变参考电流。 范围控制参考电流发生器将范围控制参考电流施加到环形振荡器。 范围控制可操作地控制距离控制参考电流发生器以顺序地改变施加到环形振荡器的范围控制参考电流。 耦合到量程控制的锁定检测器比较输出频率信号和参考频率信号，并且响应于比较信号将锁定信号施加到范围控制。 响应于所施加的锁定信号，范围控制停止变化范围。 锁相环（PLL）电路根据范围控制自动扫描多个频率子范围。 控制信号被施加到电压到电流转换器，用于在设定的时间段之后选择性地将电压/电流转换器的操作模式从压缩操作模式控制到未校准的操作模式。 该控制信号也适用于量程控制，使范围控制停止变化范围。

公开(公告)号：US07453293B2

公开(公告)日：2008-11-18

申请号：US11467972

申请日：2006-08-29

Applicant: David William Boerstler ,  Eric John Lukes ,  Hiroki Kihara ,  James David Strom

Inventor： David William Boerstler ,  Eric John Lukes ,  Hiroki Kihara ,  James David Strom

IPC: H03K21/00 ,  H03K23/00 ,  H03K25/00

CPC classification number: H03K21/406 ,  G06F7/58

Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.

Abstract translation: 本发明提供一种自校正状态电路。 第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。 第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。 第一校正电路耦合到第二触发器并且被配置为产生校正输出。 第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

公开(公告)号：US07119587B2

公开(公告)日：2006-10-10

申请号：US10850400

申请日：2004-05-20

Applicant: David William Boerstler ,  Eric John Lukes ,  Hiroki Kihara ,  James David Strom

Inventor： David William Boerstler ,  Eric John Lukes ,  Hiroki Kihara ,  James David Strom

IPC: H03K21/00

CPC classification number: H03K21/406 ,  G06F7/58

Abstract: The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted to a third flip flop. In one aspect, the received value transmitted to the third flip flop comprises an unaltered received value. In another aspect, the received value transmitted to the third flip flop comprises transmitting an altered received value. This allows for an incorrect state within the state machine to change to a correct state after a few clock pulses.

Abstract translation: 本发明提供了状态校正。 从触发器接收状态电路中的第一值。 接收到的值被发送到第二触发器。 如果出现错误状况，则第二触发器内的接收值被改变。 接收到的值被发送到第三个触发器。 一方面，发送到第三触发器的接收值包括未改变的接收值。 在另一方面，发送到第三触发器的接收值包括发送改变的接收值。 这允许状态机中的错误状态在几个时钟脉冲之后变为正确的状态。

公开(公告)号：US06218901B1

公开(公告)日：2001-04-17

申请号：US09415675

申请日：1999-10-12

Applicant: Eric John Lukes ,  James David Strom ,  Dana Marie Woeste

Inventor： Eric John Lukes ,  James David Strom ,  Dana Marie Woeste

IPC: H03F345

CPC classification number: H03F3/45179 ,  H03F3/3028 ,  H03F3/45085 ,  H03F3/45937 ,  H03F3/505 ,  H03F3/68 ,  H03F2203/45476 ,  H03F2203/45612 ,  H03F2203/45648 ,  H03F2203/45696 ,  H03K19/017563 ,  H03K19/018528

Abstract: A high speed differential output driver is provided with increased voltage swing and predrive common mode adjustment. The high speed differential output driver includes a differential input with a voltage amplifier receiving the differential input signal and a common mode adjustment signal and providing an adjustable voltage amplified signal. An emitter follower is coupled to the voltage amplifier. The emitter follower provides a level shifted voltage amplified signal. A driver is coupled to the emitter follower receiving the level shifted voltage amplified signal and providing a driver output signal.

Abstract translation: 提供高速差分输出驱动器，具有增加的电压摆幅和预调制共模调整。 高速差分输出驱动器包括具有接收差分输入信号的电压放大器和共模调整信号的差分输入，并提供可调电压放大信号。 射极跟随器耦合到电压放大器。 射极跟随器提供电平移位电压放大信号。 驱动器耦合到接收电平移位电压放大信号的发射极跟随器，并提供驱动器输出信号。

公开(公告)号：US6060939A

公开(公告)日：2000-05-09

申请号：US176140

申请日：1998-10-21

Applicant: Dana Marie Woeste ,  James David Strom

Inventor： Dana Marie Woeste ,  James David Strom

IPC: H03H11/26 ,  H03K17/62

CPC classification number: H03H11/265

Abstract: An apparatus and method for delaying a signal using a variable delay line circuit. A variable delay line circuit includes first and second delay lines, each including a plurality of delay elements. A multiplexer is coupled to respective outputs of the first and second delay lines and selectively couples the output of one of the first or second delay lines to an output of the multiplexer. A control circuit is coupled to the multiplexer and the first and second delay lines, and controls the multiplexer so as to produce a delayed signal at the multiplexer output using one of the first or second delay lines, and changes a delay factor of the other one of the first or second delay lines by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines. A reference voltage source is coupled to each of the delay elements and provides a reference voltage maintained at a substantially constant amplitude with respect to the power supply to each of the delay elements. The delayed signal may be a differential signal. Each of the delay elements may include one or more adjustable loads or adjustable current sources. An adjustable load may be implemented using P-FETs. In one embodiment, at least one of the delay elements of the first and second delay lines includes a plurality of selectable delay devices, each of which is associated with one of a plurality of selectable delay factors.

Abstract translation: 一种使用可变延迟线电路来延迟信号的装置和方法。 可变延迟线电路包括第一和第二延迟线，每条延迟线包括多个延迟元件。 多路复用器耦合到第一和第二延迟线的相应输出，并且选择性地将第一或第二延迟线之一的输出耦合到多路复用器的输出。 控制电路耦合到多路复用器和第一和第二延迟线，并且控制多路复用器，以便使用第一或第二延迟线之一在多路复用器输出端产生延迟信号，并改变另一个延迟系数的延迟因子 通过改变第一或第二延迟线中的另一个的一个或多个延迟元件的电阻和电流来控制第一或第二延迟线。 参考电压源耦合到每个延迟元件，并提供相对于每个延迟元件的电源维持在基本上恒定幅度的参考电压。 延迟信号可以是差分信号。 每个延迟元件可以包括一个或多个可调负载或可调电流源。 可以使用P-FET实现可调负载。 在一个实施例中，第一和第二延迟线的延迟元件中的至少一个包括多个可选择的延迟装置，每个延迟装置与多个可选择的延迟因子之一相关联。

公开(公告)号：US5726592A

公开(公告)日：1998-03-10

申请号：US572886

申请日：1995-12-18

Applicant: Donald Joseph Schulte ,  James David Strom

Inventor： Donald Joseph Schulte ,  James David Strom

IPC: H03F3/45 ,  H03K5/24 ,  H03K5/22

CPC classification number: H03F3/45076 ,  H03K5/2481

Abstract: A low voltage differential signal detector capable of detecting low-voltage differential signals over a large common-mode voltage range. The signal detector uses two differential pairs of opposite conductivity type, coupled to each other in a self-biasing manner to detect low voltage swings in a signal over a large common-mode voltage range. Depending upon the common-mode voltage level of the signal, the low-voltage level swings will be detected by one of the differential pairs, the other of the differential pairs or both.

Abstract translation: 一种低压差分信号检测器，能够在大的共模电压范围内检测低电压差分信号。 信号检测器使用两个相反导电类型的差分对，以自偏置方式彼此耦合，以检测大共模电压范围内的信号中的低电压摆幅。 根据信号的共模电压电平，低电压电平摆幅将由差分对之一，差分对中的另一个或两者互相检测。

公开(公告)号：US07173482B2

公开(公告)日：2007-02-06

申请号：US11094711

申请日：2005-03-30

Applicant: Katherine Ellen Lobb ,  Patrick Lee Rosno ,  James David Strom

Inventor： Katherine Ellen Lobb ,  Patrick Lee Rosno ,  James David Strom

IPC: G05F1/10

CPC classification number: G05F3/242

Abstract: A complementary metal oxide semiconductor (CMOS) voltage regulator for low headroom applications includes a differential input common mode range amplifier. The differential input common mode range amplifier is formed by a plurality of CMOS transistors. A source follower CMOS transistor is coupled to an output of the differential input common mode range amplifier for providing an output of the CMOS voltage regulator. A current source is coupled to the differential input common mode range amplifier for maintaining a bias current through the differential input common mode range amplifier.

Abstract translation: 用于低余量应用的互补金属氧化物半导体（CMOS）电压调节器包括差分输入共模范围放大器。 差分输入共模范围放大器由多个CMOS晶体管形成。 源极跟随器CMOS晶体管耦合到差分输入共模范围放大器的输出，用于提供CMOS电压调节器的输出。 电流源耦合到差分输入共模范围放大器，用于保持偏置电流通过差分输入共模范围放大器。