公开(公告)号：US5867699A

公开(公告)日：1999-02-02

申请号：US686258

申请日：1996-07-25

申请人： John S. Kuslak ,  David C. Johnson ,  Gary J. Lucas ,  Kenneth L. Engelbrecht

发明人： John S. Kuslak ,  David C. Johnson ,  Gary J. Lucas ,  Kenneth L. Engelbrecht

IPC分类号： G06F9/26 ,  G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/382 ,  G06F9/264 ,  G06F9/30054 ,  G06F9/3804

摘要： Method and apparatus for changing the sequential execution of instructions in a pipelined instruction processor by using a microcode controlled redirect controller. The execution of a redirect instruction by the pipelined instruction processor provides a number of microcode bits including a target address to the redirect controller, a predetermined combination of the microcode bits then causes the redirect controller to redirect the execution sequence of the instructions from the next sequential instruction to a target instruction.

摘要翻译： 用于通过使用微码控制的重定向控制器来改变流水线指令处理器中的指令的顺序执行的方法和装置。 由流水线指令处理器执行重定向指令向重定向控制器提供包括目标地址的多个微代码位，微代码位的预定组合然后使重定向控制器将指令的执行顺序从下一个顺序 指令到目标指令。

公开(公告)号：US6108761A

公开(公告)日：2000-08-22

申请号：US26840

申请日：1998-02-20

申请人： David C. Johnson ,  John S. Kuslak ,  Gary J. Lucas

发明人： David C. Johnson ,  John S. Kuslak ,  Gary J. Lucas

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F9/3844 ,  G06F9/322

摘要： A method and apparatus for reducing processor response time to selected transfer instructions in an multi-instruction processor. The response time is shortened by using a fast path to generate addresses for selected transfer instructions. In this fast path a base address, retained in a register from a previous instruction, is summed with an offset from the current instruction to obtain an absolute address for memory accessing. Before the fast path is entered determinations are made whether the instruction is a particular transfer instruction of a particular class and subclass, and whether the base address is different than the base address for the previous instruction. Even through the fast path is entered the usual absolute address generator path is also entered where the instruction is subjected to both high and low limit tests. If the high and low limit test determine a different base is to be used, the absolute address from the main address generator is used, instead of the absolute address from the LXJ fast path, and the system is restored to the conditions that would have prevailed if the fast path had not been entered.

摘要翻译： 一种用于在多指令处理器中减少对所选择的传送指令的处理器响应时间的方法和装置。 通过使用快速路径为选定的传输指令生成地址来缩短响应时间。 在这个快速路径中，保留在先前指令的寄存器中的基址与当前指令的偏移相加，以获得用于存储器访问的绝对地址。 在进入快速路径之前，确定指令是否是特定类和子类的特定传输指令，以及基址是否与先前指令的基址不同。 即使通过快速路径，也会进入通常的绝对地址生成器路径，其中指令经受高低限测试。 如果使用高低限测试确定不同的基准，则使用主地址生成器的绝对地址，而不是LXJ快速路径的绝对地址，并将系统恢复到将占用的条件 如果快速路径没有输入。

公开(公告)号：US5905881A

公开(公告)日：1999-05-18

申请号：US972985

申请日：1997-11-19

申请人： Nguyen T. Tran ,  John S. Kuslak ,  Lawrence R. Fontaine ,  Kenneth L. Engelbrecht

发明人： Nguyen T. Tran ,  John S. Kuslak ,  Lawrence R. Fontaine ,  Kenneth L. Engelbrecht

IPC分类号： G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/3861

摘要： An apparatus for and method of providing a data processing system that delays the writing of an architectural state change value to a corresponding architectural state register for a predetermined period of time. This may provide the instruction processor with enough time to determine if the architectural state change is valid before the architectural state change is actually written to the appropriate architectural state register.

摘要翻译： 一种用于提供数据处理系统的装置和方法，所述数据处理系统将架构状态改变值的写入在预定时间段内延迟到对应的架构状态寄存器。 这可以在架构状态改变实际上被写入适当的架构状态寄存器之前，为指令处理器提供足够的时间来确定架构状态改变是否有效。

公开(公告)号：US07673190B1

公开(公告)日：2010-03-02

申请号：US11226803

申请日：2005-09-14

申请人： Kenneth L. Engelbrecht ,  Lawrence R. Fontaine ,  John S. Kuslak ,  Conrad S. Shimada

发明人： Kenneth L. Engelbrecht ,  Lawrence R. Fontaine ,  John S. Kuslak ,  Conrad S. Shimada

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3812 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3865 ,  G06F9/3867 ,  G06F9/3873 ,  G06F11/0721 ,  G06F11/1064 ,  G06F12/0802

摘要： A system and method are provided for detecting and recovering from errors in an Instruction Cache RAM and/or Operand Cache RAM of an electronic data processing system. In some cases, errors in the Instruction Cache RAM and/or Operand Cache RAM are detected and recovered from without any required interaction of an operating system of the data processing system. Thus, and in many cases, errors in the Instruction Cache RAM and/or Operand Cache RAM can be handled seamlessly and efficiently, without requiring a specialized operating system routine, or in some cases, a maintenance technician, to help diagnose and/or fix the error.

摘要翻译： 提供了一种系统和方法，用于检测和恢复电子数据处理系统的指令高速缓存RAM和/或操作数高速缓存RAM中的错误。 在某些情况下，指令高速缓存RAM和/或操作数缓存RAM中的错误从数据处理系统的操作系统的任何必需的交互中被检测和恢复。 因此，在许多情况下，指令高速缓存RAM和/或操作数高速缓存RAM中的错误可以无缝和高效地处理，而不需要专门的操作系统程序，或者在某些情况下，维护技术人员帮助诊断和/或修复 错误。

公开(公告)号：US20100131796A1

公开(公告)日：2010-05-27

申请号：US12641014

申请日：2009-12-17

申请人： Kenneth L. Engelbrecht ,  Lawrence R. Fontaine ,  John S. Kuslak ,  Conrad S. Shimada

发明人： Kenneth L. Engelbrecht ,  Lawrence R. Fontaine ,  John S. Kuslak ,  Conrad S. Shimada

IPC分类号： G06F11/14 ,  G06F11/10 ,  G06F12/08

CPC分类号： G06F11/0793 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3812 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3865 ,  G06F9/3867 ,  G06F9/3873 ,  G06F11/0721 ,  G06F11/1064 ,  G06F12/0802

摘要： A system and method are provided for detecting and recovering from errors in an Instruction Cache RAM and/or Operand Cache RAM of an electronic data processing system. In some cases, errors in the Instruction Cache RAM and/or Operand Cache RAM are detected and recovered from without any required interaction of an operating system of the data processing system. Thus, and in many cases, errors in the Instruction Cache RAM and/or Operand Cache RAM can be handled seamlessly and efficiently, without requiring a specialized operating system routine, or in some cases, a maintenance technician, to help diagnose and/or fix the error.

摘要翻译： 提供了一种系统和方法，用于检测和恢复电子数据处理系统的指令高速缓存RAM和/或操作数高速缓存RAM中的错误。 在某些情况下，指令高速缓存RAM和/或操作数缓存RAM中的错误从数据处理系统的操作系统的任何必需的交互中被检测和恢复。 因此，在许多情况下，指令高速缓存RAM和/或操作数高速缓存RAM中的错误可以无缝和高效地处理，而不需要专门的操作系统程序，或者在某些情况下，维护技术人员帮助诊断和/或修复 错误。

公开(公告)号：US5724533A

公开(公告)日：1998-03-03

申请号：US558246

申请日：1995-11-17

申请人： John S. Kuslak ,  Gary J. Lucas

发明人： John S. Kuslak ,  Gary J. Lucas

IPC分类号： G06F9/38 ,  G06F9/312

CPC分类号： G06F9/3802 ,  G06F9/3861

摘要： A method of and apparatus for efficiently halting the operation of the instruction processor when a cache miss is detected. Generally, this is accomplished by preventing unwanted address incrementation of an instruction address pipeline and by providing a null instruction to an instruction pipeline when a cache miss is detected. Accordingly, the present invention may eliminate a recovery period after a cache miss, thereby enhance the performance of the data processing system. Further, the present invention may eliminate recovery hardware required to support the recovery process.

摘要翻译： 当检测到高速缓存未命中时，有效地停止指令处理器的操作的方法和装置。 通常，这通过防止指令地址流水线的不期望的地址增加并且当检测到高速缓存未命中时向指令流水线提供空指令来实现。 因此，本发明可以消除高速缓存未命中之后的恢复周期，从而提高数据处理系统的性能。 此外，本发明可以消除支持恢复过程所需的恢复硬件。

公开(公告)号：US07058793B1

公开(公告)日：2006-06-06

申请号：US09468051

申请日：1999-12-20

申请人： Thomas D. Hartnett ,  John S. Kuslak ,  Gary J. Lucas

发明人： Thomas D. Hartnett ,  John S. Kuslak ,  Gary J. Lucas

IPC分类号： G06F9/40

CPC分类号： G06F9/3867 ,  G06F9/3869

摘要： A synchronous pipeline design is provided that includes a first predetermined number of fetch logic sections, or “stages”, and a second predetermined number of execution stages. Instructions are retrieved from memory and undergo instruction pre-decode and decode operations during the fetch stages of the pipeline. Thereafter, decoded instruction signals are passed to the execution stages of the pipeline, where the signals are dispatched to other execution logic sections to control operand address generation, operand retrieval, any arithmetic processing, and the storing of any generated results. Instructions advance within the various pipeline fetch stages in a manner that may be independent from the way instructions advance within the execution stages. Thus, in certain instances, instruction execution may stall such that the execution stages of the pipeline are not receiving additional instructions to process. This may occur, for example, because an operand required for instruction execution is unavailable. It may also occur for certain instructions that require additional processing cycles. Even though instructions are not entering the execution stages, instructions may continue to enter the fetch stages of the pipeline until all fetch stages are processing a respective instruction. As a result, when normal instruction execution resumes within the execution stages of the pipeline, all fetch stages of the pipeline have been filled, and pre-decode and decode operations have been completed for those instructions awaiting the entry into the execution stages of the pipeline.

摘要翻译： 提供了包括第一预定数量的取出逻辑部分或“阶段”和第二预定数量的执行阶段的同步管道设计。 从存储器检索指令，并在流水线的取出阶段进行指令预解码和解码操作。 此后，解码的指令信号被传递到流水线的执行阶段，其中信号被分派到其他执行逻辑部分以控制操作数地址生成，操作数检索，任何算术处理以及存储任何生成的结果。 指令在各种流水线提取阶段内以可能独立于执行阶段内的指令前进方式的方式进行。 因此，在某些情况下，指令执行可能停止，使得流水线的执行阶段没有接收到额外的处理指令。 这可能会发生，例如，因为指令执行所需的操作数不可用。 对于需要额外处理循环的某些指令也可能发生。 即使指令没有进入执行阶段，指令可以继续进入流水线的提取阶段，直到所有获取阶段都处理相应的指令。 因此，当正常指令执行在流水线的执行阶段中恢复时，流水线的所有提取阶段已经被填充，并且对于等待进入流水线执行阶段的那些指令已经完成了预解码和解码操作 。

公开(公告)号：US5761740A

公开(公告)日：1998-06-02

申请号：US566116

申请日：1995-11-30

申请人： David C. Johnson ,  Lawrence R. Fontaine ,  John S. Kuslak

发明人： David C. Johnson ,  Lawrence R. Fontaine ,  John S. Kuslak

IPC分类号： G06F9/355 ,  G06F12/08 ,  G06F9/26 ,  G06F12/06

CPC分类号： G06F9/30047 ,  G06F12/0875 ,  G06F9/342

摘要： A method of and apparatus for rapidly modifying the user base registers of an instruction processor. In accordance with the present invention, a load base register user instruction may request an operand from a cache memory, wherein the requested operand may provide a new L field and a new bank descriptor index field. An unconditional compare may be made between the new L,BDI fields and the prior L,BDI fields, regardless of whether the requested operand providing the new L,BDI fields actually resides in a corresponding operand cache. In parallel therewith, the operand cache may determine whether or not the requested operand that provided the new L,BDI fields actually resides in the cache memory. A selector block may then determine if the new L,BDI fields match the previous L,BDI fields, and if the requested operand that provided the new L,BDI fields actually resides in the cache memory. If so, a fast load base register algorithm may be used to load the base register. If not, a slow load base register algorithm may be used.

摘要翻译： 一种用于快速修改指令处理器的用户基本寄存器的方法和装置。 根据本发明，负载基址寄存器用户指令可以从高速缓存存储器请求操作数，其中所请求的操作数可以提供新的L字段和新的存储体描述符索引字段。 可以在新的L，BDI字段和先前的L，BDI字段之间进行无条件比较，而不管提供新的L，BDI字段的请求操作数是否实际驻留在相应的操作数高速缓存中。 与此同时，操作数高速缓存可以确定提供新的L，BDI字段的所请求的操作数是否实际驻留在高速缓冲存储器中。 选择器块然后可以确定新的L，BDI字段是否与先前的L，BDI字段匹配，并且如果提供新的L，BDI字段的所请求的操作数实际驻留在高速缓冲存储器中。 如果是这样，可以使用快速加载基址寄存器算法来加载基址寄存器。 如果不是，则可以使用缓慢的负载基址寄存器算法。

公开(公告)号：US07389407B1

公开(公告)日：2008-06-17

申请号：US10278559

申请日：2002-10-23

申请人： John S. Kuslak ,  Thomas D. Hartnett

发明人： John S. Kuslak ,  Thomas D. Hartnett

IPC分类号： G06F15/00

CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3869

摘要： A method and apparatus to control logic sections of a pipeline instruction processor is disclosed. A state machine is provided that models the flow of instructions through the pipeline. The state machine is capable of modeling execution for all combinations of instruction types that may be present within the pipeline at a given time. The state machine also models various events that affect the way instruction execution is overlapped within the pipeline, and other system occurrences that may cause the termination of some processing activity within the pipeline. The state machine provides signals to control the various logic sections. These signals may be used to determine whether the results of processing activity within the logic sections should be retained or discarded.

摘要翻译： 公开了一种用于控制流水线指令处理器的逻辑部分的方法和装置。 提供了通过管道对指令流进行建模的状态机。 状态机能够对给定时间内可能存在于管道中的指令类型的所有组合进行建模。 状态机还对影响指令执行在管道中重叠的方式的各种事件进行建模，以及可能导致流水线内某些处理活动终止的其他系统事件。 状态机提供信号来控制各种逻辑部分。 这些信号可用于确定逻辑部分内处理活动的结果是否应保留或丢弃。

公开(公告)号：US6167479A

公开(公告)日：2000-12-26

申请号：US128297

申请日：1998-08-03

申请人： Thomas D. Hartnett ,  John S. Kuslak ,  David R. Schroeder

发明人： Thomas D. Hartnett ,  John S. Kuslak ,  David R. Schroeder

IPC分类号： G06F9/318 ,  G06F9/48

CPC分类号： G06F9/30181 ,  G06F9/30065

摘要： A system and method is provided for selectively injecting interrupts within the instruction stream of a data processing system. The system includes a programmable storage device for storing interrupt injection signals, each of which is associated with a respective machine instruction. When execution of the associated machine instruction is initiated, the stored signal is read from the storage device and is made available to the interrupt logic within the instruction processor. If set to a predetermined logic level, the signal causes an interrupt to be injected within the instruction processor. The system provides the capability to simultaneously inject different types of interrupts, including fault and non-fault interrupts, during the execution of any instruction. The invention further provides a programmable means for injecting errors at predetermined intervals in the instruction stream. Because the current invention allows interrupt injection to be controlled by programmable logic within the instruction processor itself instead by stimulus generated and controlled by a simulation program as in prior art systems, there is no need to develop complex simulation programs to generate and control the external stimulus. Any simulation program can utilize the interrupt injection system to test the interrupt logic. Furthermore, the injected interrupts are handled in a manner which is transparent to the system software, which makes development of test-version interrupt handling code unnecessary. Moreover, the interrupt injection system may be used during normal (non-test) situations to place the instruction processor under microcode control. This can be useful to provide temporary fixes to hardware problems in a manner which is transparent to the operating system.

摘要翻译： 提供了一种用于在数据处理系统的指令流内选择性地注入中断的系统和方法。 该系统包括用于存储中断注入信号的可编程存储装置，每个中断注入信号与相应的机器指令相关联。 当启动相关联的机器指令的执行时，存储的信号从存储设备读取并且使其可用于指令处理器内的中断逻辑。 如果设置为预定的逻辑电平，则该信号使得在指令处理器内注入中断。 该系统提供在执行任何指令期间同时注入不同类型中断的能力，包括故障和非故障中断。 本发明还提供了一种用于在指令流中以预定间隔注入错误的可编程装置。 因为本发明允许中断注入由指令处理器本身内的可编程逻辑来控制，而不是如现有技术系统中由仿真程序生成和控制的刺激，所以不需要开发复杂的模拟程序来产生和控制外部刺激 。 任何仿真程序都可以利用中断注入系统来测试中断逻辑。 此外，注入的中断以对系统软件透明的方式进行处理，这使得不需要开发测试版本的中断处理代码。 此外，在正常（非测试）情况下可以使用中断注入系统以将指令处理器置于微代码控制下。 这对于以对操作系统是透明的方式提供对硬件问题的临时修复是有用的。