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    Isolation technique for silicon germanium devices
    1.
    发明授权
    Isolation technique for silicon germanium devices 失效
    硅锗器件的隔离技术

    公开(公告)号：US5266813A

    公开(公告)日：1993-11-30

    申请号：US825230

    申请日：1992-01-24

    申请人： James H. Comfort ,  David L. Harame ,  Scott R. Stiffler

    发明人： James H. Comfort ,  David L. Harame ,  Scott R. Stiffler

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L31/12

    CPC分类号： H01L21/763 ,  H01L21/76224

    摘要： The present invention is an isolation structure for use with FET or bipolar devices incorporating a silicon-germanium layer in which the semiconductor devices are isolated by trench structures. A trench is etched through a pad layer, a single crystal silicon layer, a silicon-germanium layer, and finally, into the silicon substrate. The silicon-germanium layer is interposed between the single crystal silicon layer and the silicon substrate and the pad layer covers the single crystal silicon layer. The trench sidewall exposes the silicon-germanium layer. A single crystal silicon layer is formed as a trench liner. This silicon trench liner is then oxidized to passivate the trench isolation. The trench can then be filled with a dielectric without the devices being affected by parasitic leakage caused by the silicon-germanium layer exposed by the trench isolation.

    Isolation technique for silicon germanium devices
    2.
    发明授权
    Isolation technique for silicon germanium devices 失效
    硅锗器件的隔离技术

    公开(公告)号：US5308785A

    公开(公告)日：1994-05-03

    申请号：US115509

    申请日：1993-09-01

    申请人： James H. Comfort ,  David L. Harame ,  Scott R. Stiffler

    发明人： James H. Comfort ,  David L. Harame ,  Scott R. Stiffler

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

    CPC分类号： H01L21/763 ,  H01L21/76224

    摘要： The present invention is an isolation structure for use with FET or bipolar devices incorporating a silicon-germanium layer in which the semiconductor devices are isolated by trench structures. A trench is etched through a pad layer, a single crystal silicon layer, a silicon-germanium layer, and finally, into the silicon substrate. The silicon-germanium layer is interposed between the single crystal silicon layer and the silicon substrate and the pad layer covers the single crystal silicon layer. The trench sidewall exposes the silicon-germanium layer. A single crystal silicon layer is formed as a trench liner. This silicon trench liner is then oxidized to passivate the trench isolation. The trench can then be filled with a dielectric without the devices being affected by parasitic leakage caused by the silicon-germanium layer exposed by the trench isolation.

    摘要翻译： 本发明是一种用于FET或双极器件的隔离结构，其中半导体器件通过沟槽结构隔离而结合有硅 - 锗层。 通过衬垫层，单晶硅层，硅 - 锗层蚀刻沟槽，最后蚀刻到硅衬底中。 硅 - 锗层介于单晶硅层和硅衬底之间，衬垫层覆盖单晶硅层。 沟槽侧壁露出硅 - 锗层。 形成单晶硅层作为沟槽衬垫。 然后将该硅沟槽衬垫氧化以钝化沟槽隔离。 然后可以用电介质填充沟槽，而不会受到由沟槽隔离暴露的硅 - 锗层引起的寄生泄漏的影响。

    Isolated sidewall capacitor
    3.
    发明授权
    Isolated sidewall capacitor 失效
    隔离侧壁电容器

    公开(公告)号：US6027966A

    公开(公告)日：2000-02-22

    申请号：US910179

    申请日：1997-08-13

    申请人： Katherine Lynn Saenger ,  James H. Comfort ,  Alfred Grill ,  David Edward Kotecki

    发明人： Katherine Lynn Saenger ,  James H. Comfort ,  Alfred Grill ,  David Edward Kotecki

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/70

    CPC分类号： H01L28/55 ,  H01L27/10852 ,  Y10T29/435

    摘要： A capacitor structure is provided, with a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening.

    摘要翻译： 提供一种电容器结构，其中第一导体位于衬底的顶部，第一非导体位于第一导体之上，并且基本上与第一导体对准，第一导体和第一非导体具有形成在其中的第一开口， 形成在第一开口中的导电侧壁间隔物，其中形成有第二开口的非导电侧壁隔离物和形成在第二开口中的第二导体。

    Low capacitance bipolar junction transistor and fabrication process therfor
    6.
    发明授权
    Low capacitance bipolar junction transistor and fabrication process therfor 失效
    低电容双极性晶体管和制造工艺

    公开(公告)号：US5117271A

    公开(公告)日：1992-05-26

    申请号：US624018

    申请日：1990-12-07

    申请人： James H. Comfort ,  Tze-Chiang Chen ,  Pong-Fei Lu ,  Bernard S. Meyerson ,  Yuan-Chen Sun ,  Denny D. Tang

    发明人： James H. Comfort ,  Tze-Chiang Chen ,  Pong-Fei Lu ,  Bernard S. Meyerson ,  Yuan-Chen Sun ,  Denny D. Tang

    IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L21/762 ,  H01L29/732

    CPC分类号： H01L29/66287 ,  H01L21/28525 ,  H01L21/76229 ,  H01L29/66242

    摘要： This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-aligned elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferable polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.