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1.发明授权Data speculation based on addressing patterns identifying dual-purpose register 失效基于识别双用途寄存器的寻址模式的数据推测公开(公告)号：US07024537B2
公开(公告)日：2006-04-04
申请号：US10348144
申请日：2003-01-21
IPC分类号： G06F12/10
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3832
摘要： A system may include a memory file and an execution core. The memory file may include an entry configured to store an addressing pattern and a tag. If an addressing pattern of a memory operation matches the addressing pattern stored in the entry, the memory file may be configured to link a data value identified by the tag to a speculative result of the memory operation. The addressing pattern of the memory operation includes an identifier of a logical register, and the memory file may be configured to predict whether the logical register is being specified as a general purpose register or a stack frame pointer register in order to determine whether the addressing pattern of the memory operation matches the addressing pattern stored in the entry. The execution core may be configured to access the speculative result when executing another operation that is dependent on the memory operation.
摘要翻译： 系统可以包括存储器文件和执行核心。 存储器文件可以包括被配置为存储寻址模式和标签的条目。 如果存储器操作的寻址模式与存储在条目中的寻址模式相匹配，则存储器文件可以被配置为将由标签识别的数据值链接到存储器操作的推测结果。 存储器操作的寻址模式包括逻辑寄存器的标识符，并且存储器文件可以被配置为预测逻辑寄存器是否被指定为通用寄存器或堆栈帧指针寄存器，以便确定寻址模式 的存储器操作匹配存储在条目中的寻址模式。 执行核心可以被配置为在执行取决于存储器操作的另一操作时访问推测结果。
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公开(公告)号：US07089400B1
公开(公告)日：2006-08-08
申请号：US10347822
申请日：2003-01-21
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/30134 , G06F9/345 , G06F9/3834 , G06F9/3842
摘要： A processor may include a stack file and an execution core. The stack file may include an entry configured to store an addressing pattern and a tag. The addressing pattern identifies a memory location within the stack area of memory. The stack file may be configured to link a data value identified by the tag stored in the entry to the speculative result of a memory operation if the addressing pattern of the memory operation matches the addressing pattern stored in the entry. The execution core may be configured to access the speculative result when executing another operation that is dependent on the memory operation.
摘要翻译： 处理器可以包括堆栈文件和执行核心。 堆栈文件可以包括被配置为存储寻址模式和标签的条目。 寻址模式识别存储器堆栈区域内的存储器位置。 如果存储器操作的寻址模式与存储在条目中的寻址模式匹配，则堆栈文件可以被配置为将由条目中存储的标签识别的数据值链接到存储器操作的推测结果。 执行核心可以被配置为在执行取决于存储器操作的另一操作时访问推测结果。
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3.发明授权System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation 有权用于修改加载操作以包括寄存器到寄存器移动操作的系统和方法，以将推测负载结果转发到从属操作公开(公告)号：US07222226B1
公开(公告)日：2007-05-22
申请号：US10135631
申请日：2002-04-30
IPC分类号： G06F9/312
CPC分类号： G06F9/3842 , G06F9/3017 , G06F9/3828 , G06F9/3832
摘要： A system may include a dispatch unit, a scheduler, and an execution core. The dispatch unit may be configured to modify a load operation to include a register-to-register move operation in response to an indication that a speculative result of the load operation is linked to a data value identified by a first tag. The scheduler may be coupled to the dispatch unit and configured to issue the register-to-register move operation in response to availability of the data value. The execution core may be configured to execute the register-to-register move operation by outputting the data value and a tag indicating that the data value is the result of the load operation.
摘要翻译： 系统可以包括调度单元，调度器和执行核心。 调度单元可以被配置为响应于加载操作的推测结果链接到由第一标签识别的数据值的指示，修改加载操作以包括寄存器到寄存器移动操作。 调度器可以耦合到调度单元并且被配置为响应于数据值的可用性发布寄存器到寄存器移动操作。 执行核心可以被配置为通过输出数据值和指示数据值是加载操作的结果的标签来执行寄存器到寄存器移动操作。
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4.发明授权System and method of using speculative operand sources in order to speculatively bypass load-store operations 失效使用推测操作数源的系统和方法，以推测绕过加载存储操作公开(公告)号：US06845442B1
公开(公告)日：2005-01-18
申请号：US10135497
申请日：2002-04-30
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3842
摘要： A system may include a scheduler and an execution core. The scheduler includes an entry allocated to an operation. The entry includes a non-speculative tag and a speculative tag, and both the non-speculative tag and the speculative tag are associated with a first operand of the operation. The scheduler is configured to issue the operation in response to a data value identified by the speculative tag being available. The execution core may be configured to execute the operation using the data value identified by the speculative tag. The scheduler may be configured to reissue the operation if the non-speculative tag appears on a result bus.
摘要翻译： 系统可以包括调度器和执行核心。 调度器包括分配给操作的条目。 条目包括非推测标签和推测标签，非推测标签和推测标签都与操作的第一个操作数相关联。 调度器被配置为响应于由可推测标签识别的数据值发出操作。 执行核心可以被配置为使用由推测标签识别的数据值来执行操作。 如果非推测标签出现在结果总线上，则调度器可以被配置为重新发出操作。
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5.发明授权System and method for storing performance-enhancing data in memory space freed by data compression 失效通过数据压缩将存储性能增强的数据存储在内存空间中的系统和方法公开(公告)号：US06981119B1
公开(公告)日：2005-12-27
申请号：US10230925
申请日：2002-08-29
CPC分类号： G06F12/0886 , G06F12/023 , G06F12/08 , G06F12/0862 , G06F2212/401 , G06F2212/6028
摘要： A memory system may use the storage space freed by compressing a unit of data to store performance-enhancing data associated with that unit of data. For example, a memory controller may be configured to allocate several of storage locations within a memory to store a unit of data. If the unit of data is compressed, the unit of data may not occupy a portion of the storage locations allocated to it. The memory controller may store performance-enhancing data associated with the unit of data in the portion of the storage locations allocated to but not occupied by the first unit of data.
摘要翻译： 存储器系统可以使用通过压缩数据单元而释放的存储空间来存储与该单元数据相关联的性能增强数据。 例如，存储器控制器可以被配置为在存储器内分配若干存储位置以存储数据单元。 如果数据单元被压缩，则数据单元可能不占用分配给其的存储位置的一部分。 存储器控制器可以存储与分配给但不被第一数据单元占用的存储位置的部分中的数据单元相关联的性能增强数据。
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公开(公告)号：US20090106498A1
公开(公告)日：2009-04-23
申请号：US11877311
申请日：2007-10-23
申请人： Kevin Michael Lepak , Gregory William Smaus , William A. Hughes , Vydhyanathan Kalyanasundharam
发明人： Kevin Michael Lepak , Gregory William Smaus , William A. Hughes , Vydhyanathan Kalyanasundharam
IPC分类号： G06F13/28
CPC分类号： G06F12/0862 , G06F12/0815
摘要： A system and method for obtaining coherence permission for speculative prefetched data. A memory controller stores an address of a prefetch memory line in a prefetch buffer. Upon allocation of an entry in the prefetch buffer a snoop of all the caches in the system occurs. Coherency permission information is stored in the prefetch buffer. The corresponding prefetch data may be stored elsewhere. During a subsequent memory access request for a memory address stored in the prefetch buffer, both the coherency information and prefetched data may be already available and the memory access latency is reduced.
摘要翻译： 一种用于获取推测预取数据的一致性许可的系统和方法。 存储器控制器将预取存储器行的地址存储在预取缓冲器中。 在预取缓冲区中分配条目后，会发生系统中所有缓存的窥探。 一致性许可信息存储在预取缓冲区中。 相应的预取数据可以存储在别处。 在存储在预取缓冲器中的存储器地址的后续存储器访问请求期间，一致性信息和预取数据可能已经可用，并且存储器访问等待时间减少。
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公开(公告)号：US07930485B2
公开(公告)日：2011-04-19
申请号：US11780283
申请日：2007-07-19
IPC分类号： G06F13/00
CPC分类号： G06F9/383 , G06F9/3844 , G06F12/0862
摘要： A system and method for pre-fetching data from system memory. A multi-core processor accesses a cache hit predictor concurrently with sending a memory request to a cache subsystem. The predictor has two tables. The first table is indexed by a portion of a memory address and provides a hit prediction based on a first counter value. The second table is indexed by a core number and provides a hit prediction based on a second counter value. If neither table predicts a hit, a pre-fetch request is sent to memory. In response to detecting said hit prediction is incorrect, the pre-fetch is cancelled.
摘要翻译： 一种用于从系统内存预取数据的系统和方法。 多核处理器同时向缓存子系统发送存储器请求来访问高速缓存命中预测器。 预测器有两个表。 第一个表由存储器地址的一部分索引，并且基于第一计数器值提供命中预测。 第二个表由一个核心编号索引，并提供一个基于第二个计数器值的命中预测。 如果两个表都没有预测命中，则会将预取请求发送到内存。 响应于检测到所述命中预测是不正确的，取消预取。
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公开(公告)号：US20090327616A1
公开(公告)日：2009-12-31
申请号：US12164871
申请日：2008-06-30
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F2212/2515 , Y02D10/13
摘要： A system and method for selectively transmitting probe commands and reducing network traffic. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than storing directory entries in a dedicated directory storage, directory entries may be stored in designated locations of a shared cache memory subsystem, such as an L3 cache. Directory entries are stored within the shared cache memory subsystem to provide indications of lines (or blocks) that may be cached in exclusive-modified, owned, shared, shared-one, or invalid coherency states. The absence of a directory entry for a particular line may imply that the line is not cached anywhere in a computing system.
摘要翻译： 用于选择性地发送探测命令并减少网络流量的系统和方法。 维护目录条目以过滤某些连贯事务的探测命令和响应流量。 目录条目不是将目录条目存储在专用目录存储器中，而是可以存储在共享高速缓冲存储器子系统的指定位置，例如L3高速缓存。 目录条目存储在共享高速缓冲存储器子系统内，以提供可以被排除在修改的，拥有的，共享的，共享的或无效的一致性状态中被缓存的行（或块）的指示。 没有特定行的目录条目可能意味着该行不会在计算系统的任何位置缓存。
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公开(公告)号：US08185695B2
公开(公告)日：2012-05-22
申请号：US12164871
申请日：2008-06-30
CPC分类号： G06F12/082 , G06F2212/2515 , Y02D10/13
摘要： A system and method for selectively transmitting probe commands and reducing network traffic. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than storing directory entries in a dedicated directory storage, directory entries may be stored in designated locations of a shared cache memory subsystem, such as an L3 cache. Directory entries are stored within the shared cache memory subsystem to provide indications of lines (or blocks) that may be cached in exclusive-modified, owned, shared, shared-one, or invalid coherency states. The absence of a directory entry for a particular line may imply that the line is not cached anywhere in a computing system.
摘要翻译： 用于选择性地发送探测命令并减少网络流量的系统和方法。 维护目录条目以过滤某些连贯事务的探测命令和响应流量。 目录条目不是将目录条目存储在专用目录存储器中，而是可以存储在共享高速缓冲存储器子系统的指定位置，例如L3高速缓存。 目录条目存储在共享高速缓冲存储器子系统中，以提供可以被排除在修改的，拥有的，共享的，共享的或无效的一致性状态中被缓存的行（或块）的指示。 没有特定行的目录条目可能意味着该行不会在计算系统的任何位置缓存。
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公开(公告)号：US20090024835A1
公开(公告)日：2009-01-22
申请号：US11780283
申请日：2007-07-19
IPC分类号： G06F9/40
CPC分类号： G06F9/383 , G06F9/3844 , G06F12/0862
摘要： A system and method for pre-fetching data from system memory. A multi-core processor accesses a cache hit predictor concurrently with sending a memory request to a cache subsystem. The predictor has two tables. The first table is indexed by a portion of a memory address and provides a hit prediction based on a first counter value. The second table is indexed by a core number and provides a hit prediction based on a second counter value. If neither table predicts a hit, a pre-fetch request is sent to memory. In response to detecting said hit prediction is incorrect, the pre-fetch is cancelled.
摘要翻译： 一种用于从系统内存预取数据的系统和方法。 多核处理器同时向缓存子系统发送存储器请求来访问高速缓存命中预测器。 预测器有两个表。 第一个表由存储器地址的一部分索引，并且基于第一计数器值提供命中预测。 第二个表由核心编号索引，并且基于第二计数器值提供命中预测。 如果两个表都没有预测命中，则会将预取请求发送到内存。 响应于检测到所述命中预测是不正确的，取消预取。
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