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    Selective snooping by snoop masters to locate updated data
    2.
    发明授权
    Selective snooping by snoop masters to locate updated data 失效
    通过窥探大师进行选择性窥探以查找更新的数据

    公开(公告)号：US07395380B2

    公开(公告)日：2008-07-01

    申请号：US10393116

    申请日：2003-03-20

    申请人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

    发明人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

    IPC分类号： G06F12/00 ,  G06F3/00

    CPC分类号： G06F12/0831 ,  Y02D10/13

    摘要： A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro.Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

    摘要翻译： 一种用于窥探连接到总线宏的多个窥探主机的高速缓冲存储器的方法和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但是小于所有高速缓存存储器可以具有由始发侦听器请求的数据 主站，并且其中非起始侦听主控器中的所需数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。 只有那些可能具有请求的数据的非始发侦听主机才被查询。 所有被查询的非始发侦听主人都回复。 如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。 如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

    Selective snooping by snoop masters to locate updated data
    3.
    发明授权
    Selective snooping by snoop masters to locate updated data 失效
    通过窥探大师进行选择性窥探以查找更新的数据

    公开(公告)号：US07685373B2

    公开(公告)日：2010-03-23

    申请号：US11970599

    申请日：2008-01-08

    申请人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

    发明人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0831 ,  Y02D10/13

    摘要： A system and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has a cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in an non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

    摘要翻译： 一种用于窥探连接到总线宏的多个窥探主机的高速缓存存储器的系统和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但不到全部高速缓冲存储器可具有始发请求的数据 窥探主机，其中在非始发侦听主机中所需的数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。 只有那些可能具有请求的数据的非始发侦听主机才被查询。 所有被查询的非始发侦听主人都回复。 如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。 如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

    Method and system for providing cache set selection which is power optimized
    4.
    发明授权
    Method and system for providing cache set selection which is power optimized 失效
    提供功率优化的缓存集选择的方法和系统

    公开(公告)号：US07395372B2

    公开(公告)日：2008-07-01

    申请号：US10714105

    申请日：2003-11-14

    申请人： Anthony Correale, Jr. ,  James N. Dieffenderfer ,  Robert L. Goldiez ,  Thomas P. Speier ,  William R. Reohr

    发明人： Anthony Correale, Jr. ,  James N. Dieffenderfer ,  Robert L. Goldiez ,  Thomas P. Speier ,  William R. Reohr

    IPC分类号： G06F13/00 ,  G06F1/32

    CPC分类号： G06F12/0846 ,  G06F2212/1028 ,  Y02D10/13

    摘要： A system and method for accessing a data cache having at least two ways for storing data at the same addresses. A first and second tag memory store first and second sets of tags identifying data stored in each of the ways. A translation device determines from a system address a tag identifying one of the ways. A first comparator compares tags in the address with a tag stored in the first tag memory. A second comparator compares a tag in the address with a tag stored in the second tag memory. A clock signal supplies clock signals to one or both of the ways in response to an access mode signal. The system can be operated so that either both ways of the associative data cache are clocked, in a high speed access mode, or it can apply clock signals to only one of the ways selected by an output from the first and second comparators in a power efficient mode of operation.

    摘要翻译： 一种用于访问具有至少两种在相同地址处存储数据的方式的数据高速缓存的系统和方法。 第一和第二标签存储器存储识别以每种方式存储的数据的第一和第二组标签。 翻译装置从系统地址确定识别方式之一的标签。 第一个比较器将地址中的标签与存储在第一标签存储器中的标签进行比较。 第二比较器将地址中的标签与存储在第二标签存储器中的标签进行比较。 响应于访问模式信号，时钟信号将时钟信号提供给一种或两种方式。 可以对系统进行操作，使得关联数据高速缓存的两种方式都以高速访问模式被计时，或者它可以将时钟信号仅以来自第一和第二比较器的输出的功率中的一种方式应用于时钟信号 高效的运行模式。

    Reducing latency of a snoop tenure
    6.
    发明授权
    Reducing latency of a snoop tenure 失效
    减少窥探权限的延迟

    公开(公告)号：US06976132B2

    公开(公告)日：2005-12-13

    申请号：US10249304

    申请日：2003-03-28

    申请人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

    发明人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0831

    摘要： A method and system for reducing latency of a snoop tenure. A bus macro may receive a snoopable transfer request. The bus macro may determine which snoop controllers in a system will participate in the snoop transaction. The bus macro may then identify which participating snoop controllers are passive. Passive snoop controllers are snoop controllers associated with cache memories with cache lines only in the shared or invalid states of the MESI protocol. The snoop request may then be completed by the bus macro without waiting to receive responses from the passive participating snoop controllers. By not waiting for responses from passive snoop controllers, the bus macro may be able to complete the snoop request in a shorter amount of time thereby reducing the latency of the snoop tenure and improving performance of the system bus.

    摘要翻译： 一种减少窥探权限延迟的方法和系统。 总线宏可以接收可窥探的传输请求。 总线宏可以确定系统中哪个侦听控制器将参与侦听事务。 总线宏可能会识别哪些参与侦听控制器是被动的。 被动侦听控制器是与高速缓存存储器相关联的监听控制器，其高速缓存线仅在MESI协议的共享或无效状态。 然后可以由总线宏完成窥探请求，而不等待从被动参与侦听控制器接收响应。 通过不等待来自被动侦听控制器的响应，总线宏可能能够在更短的时间内完成窥探请求，从而减少了窥探任务的延迟并提高了系统总线的性能。

    Transfer request pipeline throttling
    7.
    发明授权
    Transfer request pipeline throttling 失效
    传输请求管道节流

    公开(公告)号：US06970962B2

    公开(公告)日：2005-11-29

    申请号：US10440778

    申请日：2003-05-19

    申请人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

    发明人： James N. Dieffenderfer ,  Bernard C. Drerup ,  Jaya P. Ganasan ,  Richard G. Hofmann ,  Thomas A. Sartorius ,  Thomas P. Speier ,  Barry J. Wolford

    IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/42

    CPC分类号： G06F12/0831 ,  G06F13/4217 ,  G06F2213/0038 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N of discrete transfer requests that may be sent by a sending device and received by a receiving device prior to acknowledgment of a transfer request by the receiving device. The pipeline depth signal may be dynamically modified, enabling a receiving device to decrement or increment the pipeline depth while one or more unacknowledged requests have been made. The dynamic modifications may occur responsive to many factors, such as an instantaneous reduction in system power consumption, a bus interface performance indicator, a receiving device performance indicator or a system performance indicator.

    摘要翻译： 一种用于在计算机系统内互连设备的流水线总线接口宏的方法和系统。 该系统和方法利用流水线深度信号，其指示可以由发送设备发送并由接收设备在接收设备确认传送请求之前由接收设备发送的离散传送请求的数量N。 可以动态地修改流水线深度信号，使得接收设备在已经做出一个或多个未确认的请求时减小或增加流水线深度。 动态修改可以响应许多因素而发生，例如系统功耗的瞬时降低，总线接口性能指示器，接收设备性能指标或系统性能指标。

    APPARATUS AND METHOD FOR DECREASING THE LATENCY BETWEEN INSTRUCTION CACHE AND A PIPELINE PROCESSOR
    8.
    发明申请
    APPARATUS AND METHOD FOR DECREASING THE LATENCY BETWEEN INSTRUCTION CACHE AND A PIPELINE PROCESSOR 失效
    指令缓存和管道处理器之间延迟延迟的装置和方法

    公开(公告)号：US20080177981A1

    公开(公告)日：2008-07-24

    申请号：US11868557

    申请日：2007-10-08

    申请人： James N. Dieffenderfer ,  Richard W. Doing ,  Brian M. Stempel ,  Steven R. Testa ,  Kenichi Tsuchiya

    发明人： James N. Dieffenderfer ,  Richard W. Doing ,  Brian M. Stempel ,  Steven R. Testa ,  Kenichi Tsuchiya

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3842 ,  G06F9/3861 ,  G06F9/3867

    摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.

    摘要翻译： 一种用于在流水线处理器中执行指令的方法和装置。 由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。 当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。 执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。

    Polynomial multiplier apparatus and method
    9.
    发明授权
    Polynomial multiplier apparatus and method 失效
    多项式乘法器装置及方法

    公开(公告)号：US5734600A

    公开(公告)日：1998-03-31

    申请号：US219694

    申请日：1994-03-29

    申请人： James N. Dieffenderfer ,  James W. Dieffenderfer

    发明人： James N. Dieffenderfer ,  James W. Dieffenderfer

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5334 ,  G06F7/5336 ,  G06F7/5338

    摘要： A multiplier efficiently multiplies signed or unsigned binary polynomial operands. The multiplier includes storage means for temporary storage of a current multiplier and a current multiplicand each of which being binary polynomials, one or more Booth decoders for examining multiplier bits iteratively in predetermined groups and presenting a Booth decoder output as one set of inputs to a plurality of delta generators and a partial product delta generator. Another set of inputs to the delta generators and the partial product delta generator is a predetermined group of bits from a multiplicand. The outputs of the partial product delta generator are multiplexed with outputs of the partial product register to provide inputs of an adder array. The adder array has outputs to a parallel adder which generates partial products which are then fed back to the multiplexor. The operation of the multiplier is controlled by a state machine wherein the multiplexor selects one of a plurality of inputs to the multiplexor as output depending upon the state condition of the state machine.

    摘要翻译： 乘数有效地乘以带符号或无符号的二进制多项式操作数。 乘法器包括用于临时存储当前乘法器的存储装置和每个都是二进制多项式的当前乘法器，一个或多个布尔解码器，用于在预定组中迭代地检查乘法器位，并将布斯解码器输出作为一组输入提供给多个 的三角洲发电机和部分产品增量发生器。 来自增量发生器和部分乘积增量发生器的另一组输入是来自被乘数的预定比特组。 部分乘积增量发生器的输出与部分乘积寄存器的输出复用，以提供加法器阵列的输入。 加法器阵列具有输出到并行加法器，该并行加法器产生部分积，然后反馈给多路复用器。 乘法器的操作由状态机控制，其中多路复用器根据状态机的状态来选择多路复用器的多个输入中的一个作为输出。

    VME bus transferring system broadcasting modifiers to multiple devices and the multiple devices simultaneously receiving data synchronously to the modifiers without acknowledging the modifiers
    10.
    发明授权
    VME bus transferring system broadcasting modifiers to multiple devices and the multiple devices simultaneously receiving data synchronously to the modifiers without acknowledging the modifiers 失效
    VME总线将系统广播修改器传输到多个设备，并且多个设备同时接收数据到修改器的数据，而无需确认修改器

    公开(公告)号：US5590372A

    公开(公告)日：1996-12-31

    申请号：US913270

    申请日：1992-07-14

    申请人： James N. Dieffenderfer ,  Bruce J. Morehead

    发明人： James N. Dieffenderfer ,  Bruce J. Morehead

    IPC分类号： G06F13/42 ,  G06F12/02

    CPC分类号： G06F13/4213

    摘要： A method for synchronous broadcasting of multiple bytes over a VME bus broadcasts multiple bytes of data across the VME bus using hardware which interfaces between the bus and attached devices. An VME address modifier code is used to identify the type of broadcast and is sent by a master device, without requiring any response from the slave devices. In a first type of broadcast an address location is transmitted over the address bus and a data message is transmitted over the data bus. In a second type of broadcast data messages are transmitted over both the data and the address buses. Multiple broadcast cycles are used to transmit the desired amount of data. An address strobe qualifies the address and data buses for a message broadcast cycle and is used by the receiving slave to clock in the message.

    摘要翻译： 一种用于通过VME总线同步广播多个字节的方法通过使用总线和附加设备之间的接口的硬件在VME总线上广播多个字节的数据。 VME地址修改码用于标识广播的类型并由主设备发送，而不需要来自从设备的任何响应。 在第一类广播中，通过地址总线传送地址位置，并通过数据总线发送数据消息。 在第二种类型的广播数据消息通过数据和地址总线发送。 使用多个广播周期来传送期望的数据量。 地址选通符限定了消息广播周期的地址和数据总线，并且被接收从机用于消息中的时钟。