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    Structure for performance improvement in vertical bipolar transistors
    1.
    发明授权
    Structure for performance improvement in vertical bipolar transistors 有权
    垂直双极晶体管性能改进的结构

    公开(公告)号：US07898061B2

    公开(公告)日：2011-03-01

    申请号：US11741436

    申请日：2007-04-27

    申请人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

    发明人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

    IPC分类号： H01L29/73

    CPC分类号： H01L29/7371 ,  H01L27/0823 ,  H01L29/66242

    摘要： A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.

    摘要翻译： 提供了形成其中具有两个不同应变的半导体器件的方法。 该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。 第一或第二应变中的任一种可以是拉伸的或压缩的。 此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。 特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。

    Structure and method for performance improvement in vertical bipolar transistors
    2.
    发明授权
    Structure and method for performance improvement in vertical bipolar transistors 有权
    垂直双极晶体管性能改进的结构和方法

    公开(公告)号：US07932155B2

    公开(公告)日：2011-04-26

    申请号：US11760288

    申请日：2007-06-08

    申请人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

    发明人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

    IPC分类号： H01L21/8222

    CPC分类号： H01L29/7371 ,  H01L27/0823 ,  H01L29/66242

    摘要： A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.

    摘要翻译： 提供了形成其中具有两个不同应变的半导体器件的方法。 该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。 第一或第二应变中的任一种可以是拉伸的或压缩的。 此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。 特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。

    Structure and method for performance improvement in vertical bipolar transistors
    3.
    发明授权
    Structure and method for performance improvement in vertical bipolar transistors 有权
    垂直双极晶体管性能改进的结构和方法

    公开(公告)号：US07262484B2

    公开(公告)日：2007-08-28

    申请号：US10908361

    申请日：2005-05-09

    申请人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

    发明人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

    IPC分类号： H01L29/73

    CPC分类号： H01L29/7371 ,  H01L27/0823 ,  H01L29/66242

    摘要： A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.

    摘要翻译： 提供了形成其中具有两个不同应变的半导体器件的方法。 该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。 第一或第二应变中的任一种可以是拉伸的或压缩的。 此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。 特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。

    Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same
    4.
    发明授权
    Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 失效
    双极晶体管具有可选择的自对准的外部基极和其形成方法

    公开(公告)号：US07253096B2

    公开(公告)日：2007-08-07

    申请号：US11289915

    申请日：2005-11-30

    申请人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

    发明人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

    摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

    摘要翻译： 公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。 制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。 然后通过在第一非本征基层上的光刻形成电介质着色焊盘。 接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。 通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

    Diffused extrinsic base and method for fabrication
    7.
    发明授权
    Diffused extrinsic base and method for fabrication 失效
    扩散的外在基础和制造方法

    公开(公告)号：US06869854B2

    公开(公告)日：2005-03-22

    申请号：US10064476

    申请日：2002-07-18

    申请人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

    发明人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

    IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/10 ,  H01L23/62

    CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L29/1004

    摘要： The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.

    摘要翻译： 本发明提供了在集成双极性电路器件中提供增加的晶体管性能的独特的器件结构和方法。 本发明的优选实施例通过提供降低的基极电阻来提供改进的高速性能。 优选的设计通过将掺杂剂从掺杂剂源层扩散到外部碱性区域中形成外部碱基。 掺杂剂的这种扩散形成至少一部分外在碱。 特别地，通过扩散形成与本征基区相邻的部分。 该解决方案避免了植入外在基础的传统解决方案所引起的问题。 具体地说，通过扩散形成外部基体的至少一部分，能够使基部区域的损伤问题最小化。 这种降低的损伤增强了掺杂剂扩散到本征基质中。 另外，形成的外部基极可以具有改善的电阻，导致双极器件的最大频率改善。 另外，外部基座可以通过降低制造复杂性的自对准制造工艺来形成。

    Method for epitaxial bipolar BiCMOS
    10.
    发明授权
    Method for epitaxial bipolar BiCMOS 失效
    外延双极BiCMOS的方法

    公开(公告)号：US06448124B1

    公开(公告)日：2002-09-10

    申请号：US09439067

    申请日：1999-11-12

    申请人： Douglas D. Coolbaugh ,  James S. Dunn ,  Peter J. Geiss ,  Peter B. Gray ,  David L. Harame ,  Kathryn T. Schonenberg ,  Stephen A. St. Onge ,  Seshadri Subbanna

    发明人： Douglas D. Coolbaugh ,  James S. Dunn ,  Peter J. Geiss ,  Peter B. Gray ,  David L. Harame ,  Kathryn T. Schonenberg ,  Stephen A. St. Onge ,  Seshadri Subbanna

    IPC分类号： H01L218238

    CPC分类号： H01L21/76224 ,  H01L21/763 ,  H01L21/8249

    摘要： A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.

    摘要翻译： 提供一种形成BiCMOS集成电路的方法，其包括以下步骤：（a）在衬底的第一区域中形成双极器件的第一部分; （b）在所述第一区域上形成第一保护层以保护所述双极器件的所述第一部分; （c）在所述衬底的第二区域中形成场效应晶体管器件; （d）在所述衬底的所述第二区域上形成第二保护层以保护所述场效应晶体管器件; （e）去除所述第一保护层; （f）在所述衬底的所述第一区域中形成所述双极器件的第二部分; 和（g）去除所述第二保护层。