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    Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same
    1.
    发明授权
    Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 失效
    双极晶体管具有可选择的自对准的外部基极和其形成方法

    公开(公告)号：US07253096B2

    公开(公告)日：2007-08-07

    申请号：US11289915

    申请日：2005-11-30

    申请人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

    发明人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

    摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

    摘要翻译： 公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。 制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。 然后通过在第一非本征基层上的光刻形成电介质着色焊盘。 接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。 通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

    Method for creation of a very narrow emitter feature
    3.
    发明授权
    Method for creation of a very narrow emitter feature 失效
    用于创建非常窄的发射器特征的方法

    公开(公告)号：US06858485B2

    公开(公告)日：2005-02-22

    申请号：US10249780

    申请日：2003-05-07

    申请人： Gregory G. Freeman ,  Marwan H. Khater ,  Francois Pagette ,  Andreas D. Stricker

    发明人： Gregory G. Freeman ,  Marwan H. Khater ,  Francois Pagette ,  Andreas D. Stricker

    IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L21/8238

    CPC分类号： H01L29/66287 ,  H01L29/0804 ,  H01L29/732

    摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped emitter formed in the surface of the intrinsic base. Form an etch stop dielectric layer over the intrinsic base layer above the collector. Form a base contact layer of a conductive material over the etch stop dielectric layer and the intrinsic base layer. Form a second dielectric layer over the base contact layer. Etch a wide window through the dielectric layer and the base contact layer stopping the etching of the window at the etch stop dielectric layer. Form an island or a peninsula narrowing the wide window leaving at least one narrowed window within the wide window. Form sidewall spacers in the either the wide window or the narrowed window. Fill the windows with doped polysilicon to form an extrinsic emitter. Form an emitter below the extrinsic emitter in the surface of the intrinsic base.

    摘要翻译： 双重多晶硅自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面上的掺杂发射极。 在收集器上方的本征基底层上形成蚀刻停止介电层。 在蚀刻停止介电层和本征基极层上形成导电材料的基底接触层。 在基底接触层上形成第二介电层。 通过介电层和基底接触层蚀刻宽窗口，停止在蚀刻停止介电层处的窗口的蚀刻。 形成一个岛屿或一个半岛，缩小广阔的窗户，在宽阔的窗口内至少留出一个狭窄的窗户。 在宽窗口或狭窄的窗户中形成侧壁间隔物。 用掺杂多晶硅填充窗口以形成外部发射极。 在本征基表面的外部发射极之下形成发射体。

    Bipolar transistor with a very narrow emitter feature
    4.
    发明授权
    Bipolar transistor with a very narrow emitter feature 失效
    双极晶体管具有非常窄的发射极特性

    公开(公告)号：US07180157B2

    公开(公告)日：2007-02-20

    申请号：US10978775

    申请日：2004-11-01

    申请人： Gregory G. Freeman ,  Marwan H. Khater ,  Francois Pagette ,  Andreas D. Stricker

    发明人： Gregory G. Freeman ,  Marwan H. Khater ,  Francois Pagette ,  Andreas D. Stricker

    IPC分类号： H01L27/082

    CPC分类号： H01L29/66287 ,  H01L29/0804 ,  H01L29/732

    摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped intrinsic emitter formed in the surface of the intrinsic base. An etch stop insulator layer overlies the intrinsic base layer above the collector. A base contact layer of a conductive material overlies the etch stop dielectric layer and the intrinsic base layer. A dielectric layer overlies the base contact layer. A wide window extends through the insulator layer and the base contact layer down to the insulator layer. An island or a peninsula is formed in the wide window leaving at least one narrowed window within the wide window, with sidewall spacers in either the wide window or the narrowed window. The narrowed windows are filled with doped polysilicon forming an extrinsic emitter with the intrinsic emitter formed below the extrinsic emitter in the surface of the intrinsic base.

    摘要翻译： 双重多晶硅，自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面的掺杂本征发射极。 蚀刻停止绝缘体层覆盖在收集器上方的本征基极层。 导电材料的基极接触层覆盖在蚀刻停止介电层和本征基极层之间。 电介质层覆盖在基底接触层上。 宽窗口延伸穿过绝缘体层和基底接触层向下延伸到绝缘体层。 在宽窗口中形成岛或半岛，在宽窗口内留下至少一个变窄的窗口，在宽窗口或狭窄窗口中具有侧壁间隔物。 变窄的窗口填充有掺杂的多晶硅，其形成外部发射极，本征发射极在本征基极表面的外部发射极之下形成。

    TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE
    9.
    发明申请
    TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE 有权
    具有侧向定义的内部基极到极端基底连接区域的晶体管结构及形成结构的方法

    公开(公告)号：US20110309471A1

    公开(公告)日：2011-12-22

    申请号：US12817249

    申请日：2010-06-17

    申请人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

    发明人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

    IPC分类号： H01L29/73 ,  H01L21/331

    CPC分类号： H01L29/732 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7378

    摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.

    摘要翻译： 公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。 结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极 电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度 发射极层）进行选择性调整，以优化晶体管性能。

    Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure
    10.
    发明授权
    Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure 有权
    具有侧壁限定的内在基极到外部基极连接区域的晶体管结构和形成该结构的方法

    公开(公告)号：US08405186B2

    公开(公告)日：2013-03-26

    申请号：US12817249

    申请日：2010-06-17

    申请人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

    发明人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

    IPC分类号： H01L21/70

    CPC分类号： H01L29/732 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7378

    摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.

    摘要翻译： 公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。 结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极 电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度 发射极层）进行选择性调整，以优化晶体管性能。