公开(公告)号：US06597050B1

公开(公告)日：2003-07-22

申请号：US09574810

申请日：2000-05-19

申请人： James Stuart Dunn ,  Peter Brian Gray ,  Kenneth Knetch Kieft, III ,  Nicholas Theodore Schmidt ,  Stephen St. onge

发明人： James Stuart Dunn ,  Peter Brian Gray ,  Kenneth Knetch Kieft, III ,  Nicholas Theodore Schmidt ,  Stephen St. onge

IPC分类号： H01L3100

CPC分类号： H01L29/872

摘要： A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.

摘要翻译： 一种接触基于硅化物的肖特基二极管的方法，包括提供与相对于保护环区域的内部边缘完全接合的硅化物的接触的步骤。 具有接触肖特基二极管的保护环的硅化物的肖特基二极管和与硅化物相对于保护环的内部边缘完全与硅化物接触的接触。

公开(公告)号：US6121122A

公开(公告)日：2000-09-19

申请号：US312945

申请日：1999-05-17

申请人： James Stuart Dunn ,  Peter Brian Gray ,  Kenneth Knetch Kieft, III ,  Nicholas Theodore Schmidt ,  Stephen St. onge

发明人： James Stuart Dunn ,  Peter Brian Gray ,  Kenneth Knetch Kieft, III ,  Nicholas Theodore Schmidt ,  Stephen St. onge

IPC分类号： H01L29/872 ,  H01L29/64 ,  H01L29/56 ,  H01L29/62

CPC分类号： H01L29/872

摘要： A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.

摘要翻译： 一种接触基于硅化物的肖特基二极管的方法，包括提供与相对于保护环区域的内部边缘完全界定的硅化物的接触的步骤。 具有接触肖特基二极管的保护环的硅化物的肖特基二极管和与硅化物相对于保护环的内部边缘完全与硅化物接触的接触。

公开(公告)号：US5705407A

公开(公告)日：1998-01-06

申请号：US691730

申请日：1996-08-02

申请人： James Stuart Dunn ,  Michael Dean Hulvey ,  Eric David Johnson ,  Robert Andrew Kertis ,  Kenneth Knetch Kieft, III ,  Albert Edson Lanpher ,  Nicholas Theodore Schmidt

发明人： James Stuart Dunn ,  Michael Dean Hulvey ,  Eric David Johnson ,  Robert Andrew Kertis ,  Kenneth Knetch Kieft, III ,  Albert Edson Lanpher ,  Nicholas Theodore Schmidt

IPC分类号： H01L21/331 ,  H01L23/482 ,  H01L29/423 ,  H01L21/265

CPC分类号： H01L29/66272 ,  H01L23/4824 ,  H01L29/42304 ,  H01L2924/0002 ,  Y10S148/01

摘要： High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.

摘要翻译： 因此，阐述了具有改进的接线选项和制造方法的高性能双极晶体管。 双极晶体管包括具有多个接触焊盘的基极接触结构，当接线到晶体管时允许多个器件布局。 例如，第一器件布局可以包括集电极 - 基极 - 发射器器件布局，而第二器件布局可以包括集电极 - 发射极 - 器件布局。 更具体地，基部接触结构至少部分地围绕发射器并且具有远离发射极延伸的整体接触焊盘。 此外，基极接触结构的部分设置在晶体管的基极区域周围的绝缘层上，而其它部分直接接触基极区域。 因此，还提出了双极晶体管的具体细节以及制造方法。

公开(公告)号：US07692271B2

公开(公告)日：2010-04-06

申请号：US11679987

申请日：2007-02-28

申请人： Frederick Gustav Anderson ,  Robert Mark Rassel ,  Nicholas Theodore Schmidt ,  Xudong Wang

发明人： Frederick Gustav Anderson ,  Robert Mark Rassel ,  Nicholas Theodore Schmidt ,  Xudong Wang

IPC分类号： H01L29/93

CPC分类号： H01L29/93 ,  H01L29/417 ,  H01L29/66174

摘要： Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced apart and not in physical contact with each other, the plurality of second regions of a second dopant type, the first dopant type different from the second dopant type; a cathode terminal electrically connected to the first region; a first anode terminal electrically connected to a first set of second regions of the plurality of second regions; and a second anode terminal electrically connected to a second set of second silicon regions of the plurality of second regions, second regions of the first set of second regions alternating with second regions of the second set of second regions.

摘要翻译： 差分结变容二极管的结构和方法。 该结构包括：形成在硅衬底中的硅第一区域，第一掺杂剂类型的第一区域; 以及与所述第一区域物理和电接触的多个硅第二区域，所述多个第二区域间隔开并且不彼此物理接触，所述多个第二掺杂剂类型的第二区域不同于 第二掺杂剂类型; 电连接到第一区域的阴极端子; 电连接到所述多个第二区域中的第一组第二区域的第一阳极端子; 以及第二阳极端子，电连接到所述多个第二区域中的第二组第二硅区域，所述第一组第二区域的第二区域与所述第二组第二区域的第二区域交替。

公开(公告)号：US20080203537A1

公开(公告)日：2008-08-28

申请号：US11679987

申请日：2007-02-28

申请人： Frederick Gustav Anderson ,  Robert Mark Rassel ,  Nicholas Theodore Schmidt ,  Xudong Wang

发明人： Frederick Gustav Anderson ,  Robert Mark Rassel ,  Nicholas Theodore Schmidt ,  Xudong Wang

IPC分类号： H01L29/93 ,  H01L21/20

CPC分类号： H01L29/93 ,  H01L29/417 ,  H01L29/66174

摘要： Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced apart and not in physical contact with each other, the plurality of second regions of a second dopant type, the first dopant type different from the second dopant type; a cathode terminal electrically connected to the first region; a first anode terminal electrically connected to a first set of second regions of the plurality of second regions; and a second anode terminal electrically connected to a second set of second silicon regions of the plurality of second regions, second regions of the first set of second regions alternating with second regions of the second set of second regions.

摘要翻译： 差分结变容二极管的结构和方法。 该结构包括：形成在硅衬底中的硅第一区域，第一掺杂剂类型的第一区域; 以及与所述第一区域物理和电接触的多个硅第二区域，所述多个第二区域间隔开并且彼此不物理接触，所述多个第二掺杂剂类型的第二区域不同于 第二掺杂剂类型; 电连接到第一区域的阴极端子; 电连接到所述多个第二区域中的第一组第二区域的第一阳极端子; 以及第二阳极端子，电连接到所述多个第二区域中的第二组第二硅区域，所述第一组第二区域的第二区域与所述第二组第二区域的第二区域交替。

公开(公告)号：US06635548B2

公开(公告)日：2003-10-21

申请号：US10046595

申请日：2001-10-26

申请人： Kerry Bernstein ,  Nicholas Theodore Schmidt ,  Anthony K. Stamper ,  Stephen Arthur St. Onge ,  Steven Howard Voldman

发明人： Kerry Bernstein ,  Nicholas Theodore Schmidt ,  Anthony K. Stamper ,  Stephen Arthur St. Onge ,  Steven Howard Voldman

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31053 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method of forming an integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the method includes depositing a first insulator layer over an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are formed in the first insulator layer, and the first insulator layer is etched to form a trench therein between the first and second conductive lines. A first conductive layer is deposited over the first and second conductive lines the said trench. A second insulator layer is deposited over the first conductive layer, and a second conductive layer is deposited over the second insulator layer. Then, a third conductive line is formed and disposed in the trench, the third conductive line overlying the second conductive barrier layer.

公开(公告)号：US06384468B1

公开(公告)日：2002-05-07

申请号：US09499577

申请日：2000-02-07

申请人： Kerry Bernstein ,  Nicholas Theodore Schmidt ,  Anthony K. Stamper ,  Stephen Arthur St. Onge ,  Steven Howard Voldman

发明人： Kerry Bernstein ,  Nicholas Theodore Schmidt ,  Anthony K. Stamper ,  Stephen Arthur St. Onge ,  Steven Howard Voldman

IPC分类号： H01L2900

CPC分类号： H01L28/40 ,  H01L21/31053 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the capacitor includes a first insulator layer overlying an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are provided in the first insulator layer and are separated by a trench defined by the first insulator layer and by sidewalls of the first and second conductive lines. A first conductive barrier layer overlies and connects the first and second conductive lines, and a second insulator layer overlies the first conductive barrier layer. A second conductive barrier layer overlies the second insulator layer, and a third conductive line is disposed in the trench and overlies the second conductive barrier layer.

摘要翻译： 公开了集成电路互连电平电容器。 在示例性实施例中，电容器包括覆盖具有有源器件的半导体衬底的互连级表面上的第一绝缘体层。 第一和第二导线设置在第一绝缘体层中，并由第一绝缘体层限定的沟槽和第一和第二导电线的侧壁分开。 第一导电阻挡层覆盖并连接第一和第二导电线，并且第二绝缘体层覆盖在第一导电阻挡层上。 第二导电阻挡层覆盖在第二绝缘体层上，并且第三导电线设置在沟槽中并覆盖在第二导电阻挡层上。