公开(公告)号：US06597050B1

公开(公告)日：2003-07-22

申请号：US09574810

申请日：2000-05-19

申请人： James Stuart Dunn ,  Peter Brian Gray ,  Kenneth Knetch Kieft, III ,  Nicholas Theodore Schmidt ,  Stephen St. onge

发明人： James Stuart Dunn ,  Peter Brian Gray ,  Kenneth Knetch Kieft, III ,  Nicholas Theodore Schmidt ,  Stephen St. onge

IPC分类号： H01L3100

CPC分类号： H01L29/872

摘要： A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.

摘要翻译： 一种接触基于硅化物的肖特基二极管的方法，包括提供与相对于保护环区域的内部边缘完全接合的硅化物的接触的步骤。 具有接触肖特基二极管的保护环的硅化物的肖特基二极管和与硅化物相对于保护环的内部边缘完全与硅化物接触的接触。

公开(公告)号：US6121122A

公开(公告)日：2000-09-19

申请号：US312945

申请日：1999-05-17

申请人： James Stuart Dunn ,  Peter Brian Gray ,  Kenneth Knetch Kieft, III ,  Nicholas Theodore Schmidt ,  Stephen St. onge

发明人： James Stuart Dunn ,  Peter Brian Gray ,  Kenneth Knetch Kieft, III ,  Nicholas Theodore Schmidt ,  Stephen St. onge

IPC分类号： H01L29/872 ,  H01L29/64 ,  H01L29/56 ,  H01L29/62

CPC分类号： H01L29/872

摘要： A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.

摘要翻译： 一种接触基于硅化物的肖特基二极管的方法，包括提供与相对于保护环区域的内部边缘完全界定的硅化物的接触的步骤。 具有接触肖特基二极管的保护环的硅化物的肖特基二极管和与硅化物相对于保护环的内部边缘完全与硅化物接触的接触。

公开(公告)号：US5705407A

公开(公告)日：1998-01-06

申请号：US691730

申请日：1996-08-02

申请人： James Stuart Dunn ,  Michael Dean Hulvey ,  Eric David Johnson ,  Robert Andrew Kertis ,  Kenneth Knetch Kieft, III ,  Albert Edson Lanpher ,  Nicholas Theodore Schmidt

发明人： James Stuart Dunn ,  Michael Dean Hulvey ,  Eric David Johnson ,  Robert Andrew Kertis ,  Kenneth Knetch Kieft, III ,  Albert Edson Lanpher ,  Nicholas Theodore Schmidt

IPC分类号： H01L21/331 ,  H01L23/482 ,  H01L29/423 ,  H01L21/265

CPC分类号： H01L29/66272 ,  H01L23/4824 ,  H01L29/42304 ,  H01L2924/0002 ,  Y10S148/01

摘要： High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.

摘要翻译： 因此，阐述了具有改进的接线选项和制造方法的高性能双极晶体管。 双极晶体管包括具有多个接触焊盘的基极接触结构，当接线到晶体管时允许多个器件布局。 例如，第一器件布局可以包括集电极 - 基极 - 发射器器件布局，而第二器件布局可以包括集电极 - 发射极 - 器件布局。 更具体地，基部接触结构至少部分地围绕发射器并且具有远离发射极延伸的整体接触焊盘。 此外，基极接触结构的部分设置在晶体管的基极区域周围的绝缘层上，而其它部分直接接触基极区域。 因此，还提出了双极晶体管的具体细节以及制造方法。

公开(公告)号：US08649153B2

公开(公告)日：2014-02-11

申请号：US13096850

申请日：2011-04-28

申请人： James Stuart Dunn ,  Zhong-Xiang He ,  Anthony Kendall Stamper

发明人： James Stuart Dunn ,  Zhong-Xiang He ,  Anthony Kendall Stamper

IPC分类号： H01G4/30

CPC分类号： H01L28/40 ,  H01G4/228 ,  H01G4/33

摘要： A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.

摘要翻译： 描述了一种片式电容器和互连布线，其集成了金属绝缘体金属（MIM）电容器，锥形通孔和通孔，其在集成电路中耦合到电容器的顶部和底部电极中的一个或两个。 描述了有形地体现在机器可读介质中的设计结构，其包括在集成电路中定义MIM电容器，锥形通孔，通孔和布线电平的计算机可读代码。

公开(公告)号：US06815802B2

公开(公告)日：2004-11-09

申请号：US10122857

申请日：2002-04-15

申请人： Jack Oon Chu ,  Douglass Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

发明人： Jack Oon Chu ,  Douglass Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC分类号： H01L27082

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

公开(公告)号：US06833299B2

公开(公告)日：2004-12-21

申请号：US10292204

申请日：2002-11-12

申请人： Douglas D. Coolbaugh ,  James Stuart Dunn ,  Stephen Arthur St. Onge

发明人： Douglas D. Coolbaugh ,  James Stuart Dunn ,  Stephen Arthur St. Onge

IPC分类号： H01L218244

CPC分类号： H01L28/40 ,  H01L29/94

摘要： A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

摘要翻译： 一种用作BiCMOS器件中的组件的堆叠多晶硅/ MOS电容器，包括在其表面形成有具有第一导电类型的区域的半导体衬底; 形成在覆盖所述第一导电型区域的所述半导体衬底上的栅极氧化物; 形成在至少所述栅极氧化物层上的第一多晶硅层，所述第一多晶硅层掺杂有N或P型掺杂剂; 形成在所述第一多晶硅层上的电介质层; 以及形成在所述介电层上的第二多晶硅层，所述第二多晶硅层掺杂有与所述第一多晶硅层相同或不同的掺杂剂。

公开(公告)号：US06507063B2

公开(公告)日：2003-01-14

申请号：US09551168

申请日：2000-04-17

申请人： Douglas D. Coolbaugh ,  James Stuart Dunn ,  Stephen Arthur St. Onge

发明人： Douglas D. Coolbaugh ,  James Stuart Dunn ,  Stephen Arthur St. Onge

IPC分类号： H01L27108

CPC分类号： H01L28/40 ,  H01L29/94

摘要： A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

摘要翻译： 一种用作BiCMOS器件中的组件的堆叠多晶硅/ MOS电容器，包括在其表面形成有具有第一导电类型的区域的半导体衬底; 形成在覆盖所述第一导电型区域的所述半导体衬底上的栅极氧化物; 形成在至少所述栅极氧化物层上的第一多晶硅层，所述第一多晶硅层掺杂有N或P型掺杂剂; 形成在所述第一多晶硅层上的电介质层; 以及形成在所述介电层上的第二多晶硅层，所述第二多晶硅层掺杂有与所述第一多晶硅层相同或不同的掺杂剂。

公开(公告)号：US06440811B1

公开(公告)日：2002-08-27

申请号：US09745361

申请日：2000-12-21

申请人： Douglas Duane Coolbaugh ,  James Stuart Dunn ,  Stephen Arthur St. Onge

发明人： Douglas Duane Coolbaugh ,  James Stuart Dunn ,  Stephen Arthur St. Onge

IPC分类号： H01L218228

CPC分类号： H01L28/40 ,  H01L27/0635

摘要： A method for fabricating a poly-poly capacitor integrated with a BiCMOS process which includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor; and forming an upper SiGe plate electrode during growth of a SiGe base region of a heterojunction bipolar transistor.

摘要翻译： 一种用于制造与BiCMOS工艺集成的多晶硅电容器的方法，包括在沉积CMOS晶体管的栅电极期间形成多晶硅电容器的下板电极; 以及在异质结双极晶体管的SiGe基区的生长期间形成上SiGe板电极。

公开(公告)号：US08375539B2

公开(公告)日：2013-02-19

申请号：US12535804

申请日：2009-08-05

申请人： James Stuart Dunn ,  Zhong-Xiang He ,  Anthony K. Stamper

发明人： James Stuart Dunn ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC分类号： H01G7/00

CPC分类号： H01G4/06 ,  H01G4/1209 ,  H01G4/232 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49156 ,  H01L2924/00

摘要： A method of manufacturing a low capacitance density, high voltage MIM capacitor and the high density MIM capacitor. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.

摘要翻译： 制造低电容密度，高电压MIM电容器和高密度MIM电容器的方法。 该方法包括沉积彼此交错的多个板和多个电介质层。 该方法还包括蚀刻多个板的最上面板的一部分，同时保护最上面的板的其它部分。 最上层的受保护的其它部分形成第一金属 - 绝缘体 - 金属（MIM）电容器的顶板，并且蚀刻暴露第二MIM电容器的顶板。

公开(公告)号：US20080124881A1

公开(公告)日：2008-05-29

申请号：US11562735

申请日：2006-11-22

申请人： Jack Ooh Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

发明人： Jack Ooh Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

摘要翻译： 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。