公开(公告)号：US06816932B2

公开(公告)日：2004-11-09

申请号：US09858778

申请日：2001-05-15

申请人： James Y. Cho ,  Joseph B. Rowlands ,  Mark H. Pearce

发明人： James Y. Cho ,  Joseph B. Rowlands ,  Mark H. Pearce

IPC分类号： G06F1338

CPC分类号： G06F13/423 ,  G06F13/4077

摘要： A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

公开(公告)号：US07076582B2

公开(公告)日：2006-07-11

申请号：US10950082

申请日：2004-09-24

申请人： James Y. Cho ,  Joseph B. Rowlands ,  Mark H. Pearce

发明人： James Y. Cho ,  Joseph B. Rowlands ,  Mark H. Pearce

IPC分类号： G06F13/38 ,  H03K19/00

CPC分类号： G06F13/423 ,  G06F13/4077

摘要： A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

公开(公告)号：US06877085B2

公开(公告)日：2005-04-05

申请号：US10068286

申请日：2002-02-06

申请人： Tse-Yu Yeh ,  Po-Yung Chang ,  Mark H. Pearce ,  Zongjian Chen

发明人： Tse-Yu Yeh ,  Po-Yung Chang ,  Mark H. Pearce ,  Zongjian Chen

IPC分类号： G06F9/312 ,  G06F9/38

CPC分类号： G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3867

摘要： A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.

摘要翻译： 处理器包括第一电路和第二电路。 第一电路被配置为提供在处理器中至少一个预留是否有效的第一指示。 响应于处理负载链接指令来建立预留，负载指令是建筑上定义用于建立预留的加载指令。 有效的预约指示由保留建立以来，由负载链接指令的目标地址指示的一个或多个字节未被更新。 第二电路被耦合以接收第一指示。 响应于第一指示，不指示有效预约，第一电路被配置为选择用于发出的推测性加载链接指令。 第二电路被配置为不响应于指示至少一个有效预留的第一指示来选择用于发出的推测性加载链接指令。 也考虑了一种方法。

公开(公告)号：US06646899B2

公开(公告)日：2003-11-11

申请号：US09957744

申请日：2001-09-21

申请人： George Kong Yiu ,  Mark H. Pearce

发明人： George Kong Yiu ,  Mark H. Pearce

IPC分类号： G11C1500

CPC分类号： G11C15/00 ,  G11C15/04

摘要： A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that CAM cell match. A circuit is configured to logically AND the outputs to generate a hit output. A first compare line generator circuit is configured to generate a first pulse responsive to a clock signal and a data signal and a second compare line generator circuit is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. A CAM may include a circuit configured to generate a pulse indicating a hit in an entry of the CAM and a latch circuit configured to capture the pulse responsive to the first clock signal and configured to clear responsive to the second clock signal. A first CAM may store a value in each entry and may further store a compare result. A second CAM may include entries corresponding to the entries in the first CAM, and each entry may be coupled to receive the indication of the compare result from the corresponding entry of the first CAM and is configured to generate a second compare result which includes the first compare result.

摘要翻译： CAM可以包括多个CAM单元。 每个CAM单元被配置为生成指示相应的输入位和存储在该CAM单元中的位是否匹配的输出。 电路被配置为逻辑与输出产生命中输出。 第一比较线发生器电路被配置为响应于时钟信号和数据信号产生第一脉冲，并且第二比较线发生器电路被配置为响应于时钟信号和数据信号的补码而产生第二脉冲。 CAM可以包括被配置为产生指示CAM入口中的命中的脉冲的电路和锁存电路，锁存电路被配置为响应于第一时钟信号捕获脉冲并被配置为响应于第二时钟信号而清除。 第一CAM可以在每个条目中存储值，并且可以进一步存储比较结果。 第二CAM可以包括对应于第一CAM中的条目的条目，并且每个条目可以被耦合以从第一CAM的相应条目接收比较结果的指示，并且被配置为生成包括第一CAM的第二比较结果 比较结果。

公开(公告)号：US07162613B2

公开(公告)日：2007-01-09

申请号：US11046454

申请日：2005-01-28

申请人： Tse-Yu Yeh ,  Po-Yung Chang ,  Mark H. Pearce ,  Zongjian Chen

发明人： Tse-Yu Yeh ,  Po-Yung Chang ,  Mark H. Pearce ,  Zongjian Chen

IPC分类号： G06F9/312

CPC分类号： G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3867

摘要： A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.

摘要翻译： 一种处理器包括第一电路和第二电路。 第一电路被配置为提供在处理器中至少一个预留是否有效的第一指示。 响应于处理负载链接指令来建立预留，负载指令是建筑上定义用于建立预留的加载指令。 有效的预约指示由保留建立以来，由负载链接指令的目标地址指示的一个或多个字节未被更新。 第二电路被耦合以接收第一指示。 响应于第一指示，不指示有效预约，第一电路被配置为选择用于发出的推测性加载链接指令。 第二电路被配置为不响应于指示至少一个有效预留的第一指示来选择用于发出的推测性加载链接指令。 也考虑了一种方法。

公开(公告)号：US06785152B2

公开(公告)日：2004-08-31

申请号：US10641130

申请日：2003-08-14

申请人： George Kong Yiu ,  Mark H. Pearce

发明人： George Kong Yiu ,  Mark H. Pearce

IPC分类号： G11C1500

CPC分类号： G11C15/00 ,  G11C15/04

摘要： A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that CAM cell match. A circuit is configured to logically AND the outputs to generate a hit output. A first compare line generator circuit is configured to generate a first pulse responsive to a clock signal and a data signal and a second compare line generator circuit is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. A CAM may include a circuit configured to generate a pulse indicating a hit in an entry of the CAM and a latch circuit configured to capture the pulse responsive to the first clock signal and configured to clear responsive to the second clock signal. A first CAM may store a value in each entry and may further store a compare result. A second CAM may include entries corresponding to the entries in the first CAM, and each entry may be coupled to receive the indication of the compare result from the corresponding entry of the first CAM and is configured to generate a second compare result which includes the first compare result.