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    SOI transistor having a reduced body potential and a method of forming the same
    1.
    发明授权
    SOI transistor having a reduced body potential and a method of forming the same 有权
    具有降低的体电位的SOI晶体管及其形成方法

    公开(公告)号：US07863171B2

    公开(公告)日：2011-01-04

    申请号：US11609995

    申请日：2006-12-13

    申请人： Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

    发明人： Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78609 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78621

    摘要： By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the body potential may be significantly reduced, thereby improving the overall performance of advanced SOI devices. In particular embodiments, the mechanism may be selectively applied to threshold voltage sensitive device areas, such as static RAM areas.

    摘要翻译： 通过将诸如碳，氟等的原子物质引入漏极和源极区域以及在体区域中，可以显着增加SOI晶体管的结漏电，从而为累积的少数族群提供增强的泄漏路径 电荷载体。 因此，体电位的波动可能会显着降低，从而提高先进的SOI器件的整体性能。 在特定实施例中，可以将机构选择性地应用于阈值电压敏感设备区域，例如静态RAM区域。

    SOI TRANSISTOR HAVING A REDUCED BODY POTENTIAL AND A METHOD OF FORMING THE SAME
    6.
    发明申请
    SOI TRANSISTOR HAVING A REDUCED BODY POTENTIAL AND A METHOD OF FORMING THE SAME 有权
    具有减少身体潜力的SOI晶体管及其形成方法

    公开(公告)号：US20070252205A1

    公开(公告)日：2007-11-01

    申请号：US11609995

    申请日：2006-12-13

    申请人： Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

    发明人： Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

    IPC分类号： H01L27/12 ,  H01L21/336

    CPC分类号： H01L29/78609 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78621

    摘要： By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the body potential may be significantly reduced, thereby improving the overall performance of advanced SOI devices. In particular embodiments, the mechanism may be selectively applied to threshold voltage sensitive device areas, such as static RAM areas.

    摘要翻译： 通过将诸如碳，氟等的原子物质引入漏极和源极区域以及在体区域中，可以显着增加SOI晶体管的结漏电，从而为累积的少数族群提供增强的泄漏路径 电荷载体。 因此，体电位的波动可能会显着降低，从而提高先进的SOI器件的整体性能。 在特定实施例中，可以将机构选择性地应用于阈值电压敏感设备区域，例如静态RAM区域。

    Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same
    7.
    发明授权
    Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same 有权
    具有嵌入式拉伸应变层的晶体管，其具有减小的偏移到栅电极的方法及其形成方法

    公开(公告)号：US07659213B2

    公开(公告)日：2010-02-09

    申请号：US11566840

    申请日：2006-12-05

    申请人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    发明人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    IPC分类号： H01L21/31 ,  H01L21/42 ,  H01L21/8222

    CPC分类号： C23C8/20 ,  C23C8/80 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    摘要： By incorporating carbon by means of ion implantation and a subsequent flash-based or laser-based anneal process, strained silicon/carbon material with tensile strain may be positioned in close proximity to the channel region, thereby enhancing the strain-inducing mechanism. The carbon implantation may be preceded by a pre-amorphization implantation, for instance on the basis of silicon. Moreover, by removing a spacer structure used for forming deep drain and source regions, the degree of lateral offset of the strained silicon/carbon material with respect to the gate electrode may be determined substantially independently from other process requirements. Moreover, an additional sidewall spacer used for forming metal silicide regions may be provided with reduced permittivity, thereby additionally contributing to an overall performance enhancement.

    摘要翻译： 通过离子注入和随后的基于闪光或基于激光的退火工艺引入碳，具有拉伸应变的应变硅/碳材料可以紧邻通道区域定位，从而增强应变诱导机制。 可以在碳注入之前进行预非晶化注入，例如基于硅。 此外，通过去除用于形成深漏极和源极区的间隔结构，应变硅/碳材料相对于栅极的横向偏移程度可以基本上独立于其它工艺要求来确定。 此外，用于形成金属硅化物区域的附加侧壁间隔物可以具有降低的介电常数，从而另外有助于整体性能提高。

    Method of forming a field effect transistor
    8.
    发明授权
    Method of forming a field effect transistor 有权
    形成场效应晶体管的方法

    公开(公告)号：US07723195B2

    公开(公告)日：2010-05-25

    申请号：US11566287

    申请日：2006-12-04

    申请人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    发明人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L29/165 ,  H01L29/66583 ,  H01L29/7834 ,  H01L29/7848

    摘要： A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.

    摘要翻译： 形成场效应晶体管的方法包括提供包括半导体材料的双轴应变层的衬底。 在半导体材料的双轴应变层上形成栅电极。 在栅电极附近形成凸起的源区和升高的漏极区。 将掺杂剂材料的离子注入到凸起的源极区域和隆起的漏极区域中，以形成扩展的源极区域和延伸的漏极区域。 此外，在形成根据本发明的实施例的场效应晶体管的方法中，可以在半导体材料层的凹部中形成栅电极。 因此，可以获得其中位于沟道区附近的源极侧沟道接触区域和漏极侧沟道接触区域受到双轴应变的场效应晶体管。

    Method of forming a field effect transistor
    10.
    发明申请
    Method of forming a field effect transistor 有权
    形成场效应晶体管的方法

    公开(公告)号：US20070254441A1

    公开(公告)日：2007-11-01

    申请号：US11566287

    申请日：2006-12-04

    申请人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    发明人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L29/165 ,  H01L29/66583 ,  H01L29/7834 ,  H01L29/7848

    摘要： A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.

    摘要翻译： 形成场效应晶体管的方法包括提供包括半导体材料的双轴应变层的衬底。 在半导体材料的双轴应变层上形成栅电极。 在栅电极附近形成凸起的源区和升高的漏极区。 将掺杂剂材料的离子注入到凸起的源极区域和隆起的漏极区域中，以形成扩展的源极区域和延伸的漏极区域。 此外，在形成根据本发明的实施例的场效应晶体管的方法中，可以在半导体材料层的凹部中形成栅电极。 因此，可以获得其中位于沟道区附近的源极侧沟道接触区域和漏极侧沟道接触区域受到双轴应变的场效应晶体管。