利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.048 秒)

    Relocatable built-in self test (BIST) elements for relocatable mixed-signal elements
    3.
    发明申请
    Relocatable built-in self test (BIST) elements for relocatable mixed-signal elements 有权
    可重定位的内置自检（BIST）元素，用于可重定位的混合信号元素

    公开(公告)号：US20060259841A1

    公开(公告)日：2006-11-16

    申请号：US11129547

    申请日：2005-05-13

    申请人： Scott Savage ,  Donald McGrath ,  Robert Waldron ,  Kenneth Richardson

    发明人： Scott Savage ,  Donald McGrath ,  Robert Waldron ,  Kenneth Richardson

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31704 ,  G01R31/3167

    摘要： An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.

    摘要翻译： 一种包括平台专用集成电路（ASIC）的基础层，混合信号功能和内置自检（BIST）功能的装置。 平台ASIC的基础层通常包括围绕平台ASIC的外围设置的多个预扩散区域。 每个预扩散区域通常被配置为金属可编程的。 混合信号功能可以包括由设置在多个预扩散区域的第一数量上的金属掩模组形成的两个或更多个子功能。 BIST功能可以形成有放置在多个预扩散区域的第二数量上的金属掩模组。 BIST功能可以被配置为测试混合信号功能并呈现指示混合信号功能的操作条件的数字信号。

    Isolated power domain core regions in platform ASICS
    4.
    发明申请
    Isolated power domain core regions in platform ASICS 失效
    平台ASICS中的隔离式电源域核心区域

    公开(公告)号：US20070145413A1

    公开(公告)日：2007-06-28

    申请号：US11318332

    申请日：2005-12-23

    申请人： Donald McGrath ,  Gregory Winn ,  Scott Savage

    发明人： Donald McGrath ,  Gregory Winn ,  Scott Savage

    IPC分类号： H01L27/10

    CPC分类号： H03K19/1736 ,  H01L27/0207 ,  H01L27/11807

    摘要： A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffused regions disposed in the platform ASIC. The predefined core region may comprise one or more metal layers defining a plurality of power regions formed according to a custom design created after the base layer is fabricated. The base layer can be customized by depositing one or more metal layers.

    摘要翻译： 一种包括基础层的平台专用集成电路（ASIC）。 基本层通常包括预定义的输入/输出（I / O）区域和预定义的核心区域。 预定义的输入/输出（I / O）区域可以包括布置在平台ASIC中的多个预扩散区域。 预定义的芯区域可以包括一个或多个限定根据在制造基层之后创建的定制设计形成的多个功率区域的金属层。 可以通过沉积一个或多个金属层来定制基层。

    Relocatable mixed-signal functions
    5.
    发明申请
    Relocatable mixed-signal functions 有权
    可重定位混合信号功能

    公开(公告)号：US20060253825A1

    公开(公告)日：2006-11-09

    申请号：US11125307

    申请日：2005-05-09

    申请人： Donald McGrath ,  Robert Waldron ,  Scott Savage ,  Kenneth Richardson

    发明人： Donald McGrath ,  Robert Waldron ,  Scott Savage ,  Kenneth Richardson

    IPC分类号： G06F17/50 ,  H03K19/173

    CPC分类号： G06F17/5045

    摘要： An apparatus that may include a base layer of a platform application specific integrated circuit (ASIC) and a mixed-signal function. The base layer of the platform application specific integrated circuit (ASIC) generally comprises a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions may be configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a number of the plurality of pre-diffused regions.

    摘要翻译： 可以包括平台专用集成电路（ASIC）的基础层和混合信号功能的装置。 平台应用专用集成电路（ASIC）的基层通常包括围绕平台ASIC的外围设置的多个预扩散区域。 每个预扩散区域可以被配置为金属可编程的。 混合信号功能可以包括由置于多个预扩散区域的多个上的金属掩模组形成的两个或更多个子功能。

    Maximum swing thin oxide levelshifter
    6.
    发明申请
    Maximum swing thin oxide levelshifter 失效

    公开(公告)号：US20060067140A1

    公开(公告)日：2006-03-30

    申请号：US10955663

    申请日：2004-09-30

    申请人： Scott Savage

    发明人： Scott Savage

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006

    摘要： An apparatus comprising a first transistor pair, second transistor pair, a third transistor pair and a fourth transistor pair. The first transistor pair may be (i) implemented as thin oxide devices and (ii) configured to receive a differential input signal. The second transistor pair may be (i) implemented as thick oxide devices and (ii) configured to generate a differential output signal in response to the differential input signal. The output signal has a voltage higher than the input signal. The third transistor pair may be (i) connected between the first and second transistor pairs and (ii) configured to protect the first transistor pair. The fourth transistor pair may be (i) connected between the third transistor pair and a ground and (ii) configured to increase an operating speed of the apparatus.

    R-cells containing CDM clamps
    7.
    发明申请
    R-cells containing CDM clamps 有权
    含有CDM夹的R细胞

    公开(公告)号：US20060259892A1

    公开(公告)日：2006-11-16

    申请号：US11126880

    申请日：2005-05-11

    申请人： Donald McGrath ,  Scott Savage

    发明人： Donald McGrath ,  Scott Savage

    IPC分类号： G06F17/50 ,  H03K19/173 ,  G06F19/00 ,  H01L25/00

    CPC分类号： H01L27/0251 ,  H01L2924/0002 ,  H03K19/173 ,  H01L2924/00

    摘要： A method for producing a chip is disclosed. A first step of the method may involve first fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step of the method may be to design a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form an electrostatic discharge clamp at a power domain crossing. A third step may include second fabricating the chip to add the upper metal layers.

    摘要翻译： 公开了一种芯片的制造方法。 该方法的第一步可以包括首先制造仅包括第一金属层并且包括第一金属层的芯片，使得芯片的芯区域具有单元阵列，每个单元具有多个晶体管。 该方法的第二步可以是响应于在第一制造开始之后产生的定制设计，在第一金属层上方设计多个上金属层，上金属层将多个单元互连以形成静电放电 夹在电源交叉口。 第三步骤可以包括第二制造芯片以添加上金属层。

    Slew based clock multiplier
    8.
    发明授权
    Slew based clock multiplier 失效

    公开(公告)号：US06664812B2

    公开(公告)日：2003-12-16

    申请号：US10116894

    申请日：2002-04-05

    申请人： Scott Savage

    发明人： Scott Savage

    IPC分类号： H03K1126

    CPC分类号： H03K5/1565

    摘要： A slew based clock multiplier which outputs a fraction of a master clock without having to use, as a reference, an edge of a higher frequency clock, and without having to use precision delay cells to delay edges of the master clock. The slew based clock multiplier can be configured to provide such an output as the result of a ratio of input current sources, a ratio of capacitors in the circuit, or as a result of a combination of the two.

    Distributed relocatable voltage regulator
    9.
    发明申请
    Distributed relocatable voltage regulator 有权
    分布式可重定位电压调节器

    公开(公告)号：US20060239052A1

    公开(公告)日：2006-10-26

    申请号：US11113615

    申请日：2005-04-25

    申请人： Donald McGrath ,  Scott Savage ,  Robert Waldron ,  Kenneth Richardson

    发明人： Donald McGrath ,  Scott Savage ,  Robert Waldron ,  Kenneth Richardson

    IPC分类号： H02M1/00

    CPC分类号： H01L27/11898 ,  H01L27/0207

    摘要： An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) configured to implement integrated circuit operations and (ii) having one or more I/O connections and one or more supply connections. A first group of the pre-diffused regions are metal-programmed and coupled to said I/O connections. A second group of the pre-diffused regions are metal-programmed and coupled to the supply connections.

    摘要翻译： 一种包括集成电路的装置，其具有（i）多个区域，每个区域预扩散并被配置为金属编程;以及（ii）多个引脚，被配置为将集成电路连接到插座。 逻辑部分可以在被配置为实现集成电路操作的集成电路（i）上实现，并且（ii）具有一个或多个I / O连接和一个或多个供电连接。 预扩散区域的第一组被金属编程并耦合到所述I / O连接。 第二组预扩散区域是金属编程的，并且耦合到电源连接。

    Method of interconnect for multi-slot metal-mask programmable relocatable function placed in an I/O region
    10.
    发明申请
    Method of interconnect for multi-slot metal-mask programmable relocatable function placed in an I/O region 失效
    用于多槽金属掩模可编程可重定位功能的互连方法放置在I / O区域中

    公开(公告)号：US20060279326A1

    公开(公告)日：2006-12-14

    申请号：US11120067

    申请日：2005-05-02

    申请人： Scott Savage ,  Robert Waldron ,  Donald McGrath ,  Kenneth Richardson

    发明人： Scott Savage ,  Robert Waldron ,  Donald McGrath ,  Kenneth Richardson

    IPC分类号： H03K19/173

    CPC分类号： H01L27/11898 ,  G06F17/5077 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC) comprising a plurality of pre-diffused regions disposed around a periphery of the platform ASIC, (B) forming two or more sub-functions of a function with a metal mask set placed over a number of the plurality of pre-diffused regions of the platform application specific integrated circuit and (C) configuring one or more connection points in each of the two or more sub-functions such that interconnections between the two or more sub-functions are tool routable in a single layer. Each of the pre-diffused regions is configured to be metal-programmable.

    摘要翻译： 一种用于互连金属掩模可编程功能的子功能的方法，其包括以下步骤：（A）形成平台应用专用集成电路（ASIC）的基层，所述平台专用集成电路（ASIC）包括围绕所述平台周围设置的多个预扩散区域 ASIC，（B）形成功能的两个或更多个子功能，其中金属掩模集放置在平台应用专用集成电路的多个预扩散区域的数量上，以及（C）配置一个或多个连接点 两个或更多个子功能中的每一个，使得两个或多个子功能之间的互连是可在单个层中可路由的工具。 每个预扩散区域被配置为金属可编程的。