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    CONTACT FOR SEMICONDUCTOR AND DISPLAY DEVICES
    1.
    发明申请
    CONTACT FOR SEMICONDUCTOR AND DISPLAY DEVICES 有权
    联系半导体和显示设备

    公开(公告)号：US20070296885A1

    公开(公告)日：2007-12-27

    申请号：US11854059

    申请日：2007-09-12

    申请人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

    发明人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

    IPC分类号： H01L21/4763 ,  G02F1/136 ,  H01L23/52

    CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1288 ,  H01L29/66765

    摘要： A device and corresponding method of fabrication thereof are disclosed, where the device provides a contact for semiconductor and display devices, the device including a substrate, a first wiring line assembly formed on the substrate, an under-layer formed on the first wiring line assembly, an organic insulating layer formed on the under-layer such that the organic insulating layer covers the under-layer, a pattern on the organic insulating layer for contact holes to expose the under-layer, etched contact holes formed in the under-layer in correspondence with the pattern such that the underlying first wiring line assembly is exposed to the outside, a cured organic insulating layer formed on the under-layer, and a second wiring line assembly formed on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the etched contact holes, and the corresponding method of fabrication including forming a first wiring line assembly on a substrate, forming an under-layer on the first wiring line assembly, forming an organic insulating layer such that the organic insulating layer covers the under-layer patterning the organic insulating layer to thereby form contact holes exposing the under-layer, etching the under-layer exposed through the contact holes such that the underlying first wiring line assembly is exposed to the outside, curing the organic insulating layer, and forming a second wiring line assembly on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the contact holes.

    摘要翻译： 公开了一种器件及其相应的制造方法，其中器件为半导体和显示器件提供接触，该器件包括衬底，形成在衬底上的第一布线组件，形成在第一布线组件上的底层 形成在下层上的有机绝缘层，使得有机绝缘层覆盖下层，在有机绝缘层上形成用于接触孔的图案，以暴露下层中形成的下层的蚀刻接触孔， 与图案对应，使得下面的第一布线组件暴露于外部，形成在下层上的固化的有机绝缘层和形成在有机绝缘层上的第二布线组件，使得第二布线组件是 通过蚀刻的接触孔连接到第一布线组件，以及相应的制造方法，包括形成第一布线组件 在第一布线组件上形成底层，形成有机绝缘层，使得有机绝缘层覆盖图案化有机绝缘层的下层，从而形成暴露下层，蚀刻的接触孔 所述下层通过所述接触孔暴露，使得所述下面的第一布线组件暴露于外部，固化所述有机绝缘层，以及在所述有机绝缘层上形成第二布线组合件，使得所述第二布线组件被连接 通过接触孔到第一布线组件。

    Contact for semiconductor and display devices
    2.
    发明授权
    Contact for semiconductor and display devices 有权
    半导体和显示设备接触

    公开(公告)号：US07580088B2

    公开(公告)日：2009-08-25

    申请号：US11854059

    申请日：2007-09-12

    申请人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

    发明人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

    IPC分类号： G02F1/136 ,  H01L21/4763

    CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1288 ,  H01L29/66765

    摘要： A device and corresponding method of fabrication thereof are disclosed, where the device provides a contact for semiconductor and display devices, the device including a substrate, a first wiring line assembly formed on the substrate, an under-layer formed on the first wiring line assembly, an organic insulating layer formed on the under-layer such that the organic insulating layer covers the under-layer, a pattern on the organic insulating layer for contact holes to expose the under-layer, etched contact holes formed in the under-layer in correspondence with the pattern such that the underlying first wiring line assembly is exposed to the outside, a cured organic insulating layer formed on the under-layer, and a second wiring line assembly formed on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the etched contact holes, and the corresponding method of fabrication including forming a first wiring line assembly on a substrate, forming an under-layer on the first wiring line assembly, forming an organic insulating layer such that the organic insulating layer covers the under-layer patterning the organic insulating layer to thereby form contact holes exposing the under-layer, etching the under-layer exposed through the contact holes such that the underlying first wiring line assembly is exposed to the outside, curing the organic insulating layer, and forming a second wiring line assembly on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the contact holes.

    摘要翻译： 公开了一种器件及其相应的制造方法，其中器件为半导体和显示器件提供接触，该器件包括衬底，形成在衬底上的第一布线组件，形成在第一布线组件上的底层 形成在下层上的有机绝缘层，使得有机绝缘层覆盖下层，在有机绝缘层上形成用于接触孔的图案，以暴露下层中形成的下层的蚀刻接触孔， 与图案对应，使得下面的第一布线组件暴露于外部，形成在下层上的固化的有机绝缘层和形成在有机绝缘层上的第二布线组件，使得第二布线组件是 通过蚀刻的接触孔连接到第一布线组件，以及相应的制造方法，包括形成第一布线组件 在第一布线组件上形成底层，形成有机绝缘层，使得有机绝缘层覆盖图案化有机绝缘层的下层，从而形成暴露下层，蚀刻的接触孔 所述下层通过所述接触孔暴露，使得所述下面的第一布线组件暴露于外部，固化所述有机绝缘层，以及在所述有机绝缘层上形成第二布线组合件，使得所述第二布线组件被连接 通过接触孔到第一布线组件。

    Contact for semiconductor and display devices
    3.
    发明授权
    Contact for semiconductor and display devices 有权
    半导体和显示设备接触

    公开(公告)号：US07271867B2

    公开(公告)日：2007-09-18

    申请号：US10273073

    申请日：2002-10-17

    申请人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

    发明人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

    IPC分类号： G02F1/1333 ,  G02F1/136

    CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1288 ,  H01L29/66765

    摘要： A device and corresponding method of fabrication thereof are disclosed, where the device provides a contact for semiconductor and display devices, the device including a substrate, a first wiring line assembly formed on the substrate, an under-layer formed on the first wiring line assembly, an organic insulating layer formed on the under-layer such that the organic insulating layer covers the under-layer, a pattern on the organic insulating layer for contact holes to expose the under-layer, etched contact holes formed in the under-layer in correspondence with the pattern such that the underlying first wiring line assembly is exposed to the outside, a cured organic insulating layer formed on the under-layer, and a second wiring line assembly formed on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the etched contact holes; and the corresponding method of fabrication including forming a first wiring line assembly on a substrate, forming an under-layer on the first wiring line assembly, forming an organic insulating layer such that the organic insulating layer covers the under-layer, patterning the organic insulating layer to thereby form contact holes exposing the under-layer, etching the under-layer exposed through the contact holes such that the underlying first wiring line assembly is exposed to the outside, curing the organic insulating layer, and forming a second wiring line assembly on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the contact holes.

    摘要翻译： 公开了一种器件及其相应的制造方法，其中器件为半导体和显示器件提供接触，该器件包括衬底，形成在衬底上的第一布线组件，形成在第一布线组件上的底层 形成在下层上的有机绝缘层，使得有机绝缘层覆盖下层，在有机绝缘层上形成用于接触孔的图案，以暴露下层中形成的下层的蚀刻接触孔， 与图案对应，使得下面的第一布线组件暴露于外部，形成在下层上的固化的有机绝缘层和形成在有机绝缘层上的第二布线组件，使得第二布线组件是 通过蚀刻的接触孔连接到第一布线组件; 以及相应的制造方法，包括在基板上形成第一布线线组件，在第一布线线路组件上形成底层，形成有机绝缘层，以使有机绝缘层覆盖下层，图案化有机绝缘层 从而形成暴露下层的接触孔，蚀刻通过接触孔暴露的下层，使得下面的第一布线线组件暴露于外部，固化有机绝缘层，并形成第二布线组件 所述有机绝缘层使得所述第二布线组合体通过所述接触孔连接到所述第一布线线组件。

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20080093600A1

    公开(公告)日：2008-04-24

    申请号：US11958230

    申请日：2007-12-17

    申请人： Min-Wook PARK ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

    发明人： Min-Wook PARK ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

    IPC分类号： H01L29/04

    CPC分类号： H01L29/41733 ,  H01L27/124

    摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

    摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

    Thin film transistor array panel and manufacturing method thereof
    5.
    发明授权
    Thin film transistor array panel and manufacturing method thereof 有权
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US07358123B2

    公开(公告)日：2008-04-15

    申请号：US11395434

    申请日：2006-03-30

    申请人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

    发明人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

    IPC分类号： H01L21/00

    CPC分类号： H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

    摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

    摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

    Thin film transistor array panel and manufacturing method thereof
    6.
    发明申请
    Thin film transistor array panel and manufacturing method thereof 有权
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US20060289965A1

    公开(公告)日：2006-12-28

    申请号：US11512805

    申请日：2006-08-30

    申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

    发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

    IPC分类号： H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

    CPC分类号： G02F1/1368 ,  G02F1/1339

    摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

    摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

    Thin film transistor array panel and manufacturing method thereof
    7.
    发明授权
    Thin film transistor array panel and manufacturing method thereof 有权

    公开(公告)号：US07320906B2

    公开(公告)日：2008-01-22

    申请号：US10922343

    申请日：2004-08-19

    申请人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

    发明人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

    IPC分类号： H01L21/84

    CPC分类号： H01L29/41733 ,  H01L27/124

    摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.