公开(公告)号：US6091731A

公开(公告)日：2000-07-18

申请号：US50879

申请日：1998-03-30

申请人： Janus Biegaj ,  Mark Aldo Bordogna ,  Mark Henry Davis ,  Dominic Dominijanni ,  Kurt Arnold Hedlund ,  Gary Lynn McElvany

发明人： Janus Biegaj ,  Mark Aldo Bordogna ,  Mark Henry Davis ,  Dominic Dominijanni ,  Kurt Arnold Hedlund ,  Gary Lynn McElvany

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L12/28

CPC分类号： H04L49/503 ,  H04L49/153 ,  H04L49/253 ,  H04L49/552 ,  H04Q11/0478 ,  H04L49/103 ,  H04L49/205 ,  H04L49/3009 ,  H04L49/555

摘要： Arrangements for controlling a data switching network fabric and for synchronizing duplicate modules of such a fabric. A control complex, for determining new virtual connections to be established, and for disconnecting existing virtual connections, is connected through data links to the network fabric of a data switch. The network fabric has internal control processors. The control complex communicates with these processors by sending control packets over a dedicated internal ATM link and virtual connections to these internal processors to control their establishment and disconnection of user virtual connections. Duplicate modules of the data switching fabric receive identical packets and, when synchronized, transmit identical packets at the same time. The synchronization process is implemented by data links between the control processors of the duplicate fabrics to report progress on the step by step synchronization of internal queues. The algorithms for routing cells are identical in the two modules so that once the modules are synchronized, they remain in synchronism because they use identical paths. Advantageously, a switch to a standby module can be made without losing any cells. Advantageously, the control complex can transmit control packets at a rate limited only by the ability of the control complex to generate the packet, the ability of the fabric control processors to receive these control packets, and the bandwidth of the data links connecting the control complex to the network fabric. Advantageously, no special buses are required for connecting the control complex to the network fabric.

摘要翻译： 用于控制数据交换网络结构和同步这种结构的重复模块的布置。 用于确定要建立的新虚拟连接以及用于断开现有虚拟连接的控制复合体通过数据链路连接到数据交换机的网络结构。 网络结构具有内部控制处理器。 控制复合体通过专用内部ATM链路发送控制数据包和与这些内部处理器的虚拟连接来与这些处理器进行通信，以控制其建立和断开用户虚拟连接。 数据交换结构的重复模块接收相同的数据包，同步时同时发送相同的数据包。 同步过程由重复结构的控制处理器之间的数据链接实现，以报告内部队列的逐步同步的进度。 用于路由单元的算法在两个模块中是相同的，使得一旦模块被同步，它们保持同步，因为它们使用相同的路径。 有利地，可以在不损失任何单元的情况下进行到备用模块的切换。 有利地，控制复合体可以以仅由控制复合体产生分组的能力限制的速率传输控制分组，结构控制处理器接收这些控制分组的能力以及连接控制复合体的数据链路的带宽 到网络结构。 有利地，不需要专门的总线来将控制复合体连接到网络结构。

公开(公告)号：US06091730A

公开(公告)日：2000-07-18

申请号：US50878

申请日：1998-03-30

申请人： Janus Biegaj ,  Mark Aldo Bordogna ,  Mark Henry Davis ,  Dominic Dominijani ,  Kurt Arnold Hedlund ,  Gary Lynn McElvany

发明人： Janus Biegaj ,  Mark Aldo Bordogna ,  Mark Henry Davis ,  Dominic Dominijani ,  Kurt Arnold Hedlund ,  Gary Lynn McElvany

IPC分类号： H04L12/56 ,  H04Q11/04

CPC分类号： H04L49/552 ,  H04L49/153 ,  H04L49/253 ,  H04L49/503 ,  H04Q11/0478 ,  H04L49/103 ,  H04L49/205 ,  H04L49/3009 ,  H04L49/555

摘要： Arrangements for controlling a data switching network fabric and for synchronizing duplicate modules of such a fabric. A control complex, for determining new virtual connections to be established, and for disconnecting existing virtual connections, is connected through data links to the network fabric of a data switch. The network fabric has internal control processors. The control complex communicates with these processors by sending control packets over a dedicated internal ATM link and virtual connections to these internal processors to control their establishment and disconnection of user virtual connections. Duplicate modules of the data switching fabric receive identical packets and, when synchronized, transmit identical packets at the same time. The synchronization process is implemented by data links between the control processors of the duplicate fabrics to report progress on the step by step synchronization of internal queues. The algorithms for routing cells are identical in the two modules so that once the modules are synchronized, they remain in synchronism because they use identical paths. Advantageously, a switch to a standby module can be made without losing any cells. Advantageously, the control complex can transmit control packets at a rate limited only by the ability of the control complex to generate the packet, the ability of the fabric control processors to receive these control packets, and the bandwidth of the data links connecting the control complex to the network fabric. Advantageously, no special buses are required for connecting the control complex to the network fabric.

摘要翻译： 用于控制数据交换网络结构和同步这种结构的重复模块的布置。 用于确定要建立的新虚拟连接以及用于断开现有虚拟连接的控制复合体通过数据链路连接到数据交换机的网络结构。 网络结构具有内部控制处理器。 控制复合体通过专用内部ATM链路发送控制数据包和与这些内部处理器的虚拟连接来与这些处理器进行通信，以控制其建立和断开用户虚拟连接。 数据交换结构的重复模块接收相同的数据包，同步时同时发送相同的数据包。 同步过程由重复结构的控制处理器之间的数据链接实现，以报告内部队列的逐步同步的进度。 用于路由单元的算法在两个模块中是相同的，使得一旦模块被同步，它们保持同步，因为它们使用相同的路径。 有利地，可以在不损失任何单元的情况下进行到备用模块的切换。 有利地，控制复合体可以以仅由控制复合体产生分组的能力限制的速率传输控制分组，结构控制处理器接收这些控制分组的能力以及连接控制复合体的数据链路的带宽 到网络结构。 有利地，不需要专门的总线来将控制复合体连接到网络结构。

公开(公告)号：US06683855B1

公开(公告)日：2004-01-27

申请号：US09143781

申请日：1998-08-31

申请人： Mark Aldo Bordogna ,  Ralf Dohmen ,  Wolfram Sturm

发明人： Mark Aldo Bordogna ,  Ralf Dohmen ,  Wolfram Sturm

IPC分类号： H04J116

CPC分类号： H04L1/0057 ,  H04J3/14 ,  H04J3/1611 ,  H04J2203/0089 ,  H04L1/0043 ,  H04L1/0083

摘要： Memory requirements and processing delays associated with the application of forward error correction in high speed optical transmissions are substantially reduced by mapping a forward error correction code on a row-by-row basis into unused overhead bytes in a high bit rate signal frame. By applying the forward error correction code to an entire row of the signal frame on a row by row basis, approximately one row needs to be stored at a time thereby reducing the total memory requirements for forward error correction processing. Using SONET as an exemplary application, approximately {fraction (1/9)}th of the entire SONET frame (e.g., one of nine rows) needs to be buffered for forward error correction processing. In an illustrative embodiment, four forward error correction (FEC) blocks are provided for each row for a total of 36 FEC blocks for a frame. Each FEC block comprises four bytes of correction bits for a total of 32 correction bits. These 32 correction bits are mapped to unused overhead and are used for correcting errors in one block of one row of a signal frame, wherein one block covers ¼th of the row. Other unused overhead bytes in the row can be used to carry error detection codes for detecting multiple errors in a row to determine when forward error correction should be disabled. For example, if a single bit error correcting code is employed, then error correction can be disabled to avoid false corrections if more than one error is detected.

摘要翻译： 通过将高速率光传输中的前向纠错码逐行地映射到高比特率信号帧中的未使用的开销字节，大大减少了与高速光传输中的前向纠错应用相关联的存储器要求和处理延迟。 通过逐行地将前向纠错码应用于信号帧的整个行，需要一次存储大约一行，从而减少前向纠错处理的总存储器要求。 使用SONET作为示例性应用，大约{部分（整个SONET帧的1/9（例如，九行中的一个）需要被缓冲用于前向纠错处理）在说明性实施例中，四个前向纠错（FEC）块 为每帧提供总共36个FEC块，每个FEC块包含四个字节的校正位，总共32个校正位，这32个校正位映射到未使用的开销，用于校正一个错误 一行信号帧的块，其中一个块覆盖该行的第十四行，该行中的其他未使用的开销字节可用于携带用于检测一行中的多个错误的错误检测码，以确定何时应禁用前向纠错。 例如，如果采用单个位错误校正码，则如果检测到多于一个错误，则可以禁用错误校正以避免错误校正。

公开(公告)号：US6081503A

公开(公告)日：2000-06-27

申请号：US942095

申请日：1997-10-01

申请人： Mark Aldo Bordogna ,  Philip Sidney Dietz ,  Joseph Elide Landry ,  Jeffrey Robert Towne ,  Warren Clifton Trested, Jr.

发明人： Mark Aldo Bordogna ,  Philip Sidney Dietz ,  Joseph Elide Landry ,  Jeffrey Robert Towne ,  Warren Clifton Trested, Jr.

IPC分类号： H04J3/00 ,  H04J3/14 ,  H04L12/24 ,  H04L12/56 ,  H04L29/14 ,  H04Q3/545 ,  H04Q11/04

CPC分类号： H04L49/552 ,  H04L49/254 ,  H04L49/255 ,  H04L49/35 ,  H04L49/555 ,  H04Q11/04 ,  H04Q11/0478 ,  H04Q3/54591 ,  H04L2012/5627 ,  H04L49/205 ,  H04L49/30 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13106 ,  H04Q2213/13166 ,  H04Q2213/13167 ,  H04Q2213/13176 ,  H04Q2213/1332 ,  H04Q2213/1334

摘要： A network element with a centralized switch fabric is able to support multiple switching functions while meeting established performance requirements by using a control system based on an embedded signal status protocol. Generally, each input signal within a transmission path is monitored to derive signal status information, which is then individually encoded and embedded within the input signal. The embedded signal status can be decoded and provided as input to control logic for processing at any point within the transmission path, as necessary. In the case of a centralized switch fabric, the control logic resolves an address of a single input signal based on the embedded signal status and provides this resolved address to the switch fabric so that the appropriate input signal can be selected. In the present invention, the control logic may be configured to support any given application, e.g., "path-in-line" protection switching, whereby each configuration of control logic constitutes an application control set that supports the performance requirements of that given application.

摘要翻译： 具有集中交换结构的网元能够通过使用基于嵌入式信号状态协议的控制系统来支持多种交换功能，同时满足已建立的性能要求。 通常，监视传输路径内的每个输入信号以导出信号状态信息，然后单独编码并嵌入在输入信号内。 嵌入式信号状态可以被解码并作为输入提供给控制逻辑，用于根据需要在传输路径内的任何点进行处理。 在集中式交换结构的情况下，控制逻辑基于嵌入的信号状态来解析单个输入信号的地址，并将该解析的地址提供给交换结构，使得可以选择适当的输入信号。 在本发明中，控制逻辑可以被配置为支持任何给定的应用，例如“在线路由”保护切换，由此控制逻辑的每个配置构成支持该给定应用的性能要求的应用控制集。

公开(公告)号：US6137790A

公开(公告)日：2000-10-24

申请号：US942096

申请日：1997-10-01

申请人： Mark Aldo Bordogna ,  Philip Sidney Dietz ,  Joseph Elide Landry ,  Jeffrey Robert Towne ,  Warren Clifton Trested, Jr.

发明人： Mark Aldo Bordogna ,  Philip Sidney Dietz ,  Joseph Elide Landry ,  Jeffrey Robert Towne ,  Warren Clifton Trested, Jr.

IPC分类号： H04M3/00 ,  H04J3/16 ,  H04L12/56 ,  H04Q3/68 ,  H04Q11/04 ,  H04Q11/00

CPC分类号： H04L49/255 ,  H04J3/1611 ,  H04L49/254 ,  H04L49/35 ,  H04L49/552 ,  H04Q11/0478 ,  H04Q3/685 ,  H04L2012/5627 ,  H04L49/30

摘要： A system for providing segmented control of a single, homogeneous routing structure, such as a switch fabric, includes application control elements that are each responsive to embedded signal status information for each of the input signals to the switch fabric. Within each of the application control elements, a configurable arrangement of selectors and control logic is used to provide domain segmented control of each of the separate switching functions for a particular application. Each application control element performs an application specific address resolution function to resolve a single address of one of the input signals based on the embedded signal status of each of the input signals. This single address is provided to the switch fabric so that the corresponding input signal can be selected at the switch fabric output. Because embedded signal status is provided locally at each selection point within the application control element, the control functions for each of the separate switching functions are decoupled, and, as a result, each of the separate switching functions can be independently controlled as a separate domain within the application control element. The single, homogeneous switch fabric simultaneously supports multiple applications in parallel because each of the application control elements is used to control a separate output from the switch fabric. Because of the one for one association between application control elements and switch fabric outputs, the switch fabric is effectively "channelized" whereby each channel of the switch fabric supports a separate application.

摘要翻译： 用于提供单个均匀路由结构（例如交换结构）的分段控制的系统包括各自响应于针对交换结构的每个输入信号的嵌入信号状态信息的应用控制元件。 在每个应用控制元件中，选择器和控制逻辑的可配置布置用于为特定应用提供每个分离的切换功能的域分段控制。 每个应用控制元件基于每个输入信号的嵌入信号状态执行特定于应用的地址解析功能，以解析输入信号之一的单个地址。 该单个地址被提供给交换结构，使得可以在交换结构输出处选择相应的输入信号。 由于嵌入式信号状态是在应用控制元件内的每个选择点处本地提供的，所以分离开关功能中的每一个的控制功能被去耦合，结果，每一个单独的开关功能可以被独立地控制为单独的域 在应用程序控制元素内。 单个均匀交换结构同时支持并行的多个应用，因为每个应用控制元素用于控制交换结构的单独输出。 由于应用控制元件和交换矩阵输出之间的一个关联，交换结构被有效地“通道化”，从而交换结构的每个通道支持单独的应用。

公开(公告)号：US20230344739A1

公开(公告)日：2023-10-26

申请号：US18344801

申请日：2023-06-29

申请人： Surekha Peri ,  Mark Aldo Bordogna ,  Job Abraham ,  Sankaradithyan Gunasekharan

发明人： Surekha Peri ,  Mark Aldo Bordogna ,  Job Abraham ,  Sankaradithyan Gunasekharan

IPC分类号： H04L43/106 ,  H04L43/0823 ,  H04L43/067

CPC分类号： H04L43/106 ,  H04L43/0847 ,  H04L43/067

摘要： Methods, apparatus, systems, and articles of manufacture to generate a timestamp are disclosed. Examples disclosed herein generate a correction factor based on a first timestamp and a second timestamp, the first timestamp generated before a first data packet is obtained by ethernet physical coding sublayer (PCS), the second timestamp generated before the first data packet is obtained by a physical ethernet port coupled to the ethernet PCS; and generate a third timestamp for a second data packet based on the correction factor and a fourth timestamp, the fourth timestamp generated by network interface circuitry for the second data packet.

公开(公告)号：US06560202B1

公开(公告)日：2003-05-06

申请号：US09123086

申请日：1998-07-27

申请人： Mark Aldo Bordogna ,  Philip Sidney Dietz ,  Joseph Elide Landry ,  Jeffrey Robert Towne ,  Warren Clifton Trested, Jr.

发明人： Mark Aldo Bordogna ,  Philip Sidney Dietz ,  Joseph Elide Landry ,  Jeffrey Robert Towne ,  Warren Clifton Trested, Jr.

IPC分类号： H04J116

CPC分类号： H04L49/255 ,  H04J3/085 ,  H04J3/12 ,  H04L49/254 ,  H04L49/55 ,  H04L2012/5627 ,  H04Q11/0478

摘要： Distributed switch fabrics can support multiple switching functions while meeting established performance requirements by using a control architecture based on multiple layers of signal status carried within signals transported through the distributed switch fabrics. More specifically, a method and apparatus is provided for controlling the selection of signals through distributed switch fabrics by deriving signal status information for the signals at any point along a transmission path and embedding the signal status information in each of the signals using multiple signal status layers. Each of the signals carries its respective signal status information as it propagates along the transmission path, so that the embedded signal status information can be selectively extracted from any of the multiple signal status layers to facilitate a selection decision at any of the distributed switch fabrics. The multiple layers of signal status can be used to provide a cumulative signal status of a particular signal as it propagates along the transmission path or the multiple layers can be used to support various combinations of status control, such as each layer being used to track a different level or type of status for the signal.

摘要翻译： 分布式交换结构可以支持多种交换功能，同时通过使用基于通过分布式交换结构传输的信号内的多层信号状态的控制架构来满足已建立的性能要求。 更具体地，提供了一种方法和装置，用于通过在沿着传输路径的任何点处导出信号的信号状态信息来控制通过分布式交换结构选择信号，并且使用多个信号状态层将信号状态信息嵌入在每个信号中 。 每个信号在沿着传输路径传播时携带其各自的信号状态信息，使得可以从多个信号状态层中的任何一个选择性地提取嵌入信号状态信息，以促进任何分布式交换结构的选择决策。 可以使用多层信号状态来提供特定信号沿着传输路径传播的累积信号状态，或者可以使用多个层来支持状态控制的各种组合，诸如用于跟踪 信号的不同级别或状态类型。

公开(公告)号：US06301228B1

公开(公告)日：2001-10-09

申请号：US09087067

申请日：1998-05-29

申请人： Mark Aldo Bordogna ,  Philip Sidney Dietz ,  Joseph Elide Landry ,  Jeffrey Robert Towne ,  Warren Clifton Trested, Jr.

发明人： Mark Aldo Bordogna ,  Philip Sidney Dietz ,  Joseph Elide Landry ,  Jeffrey Robert Towne ,  Warren Clifton Trested, Jr.

IPC分类号： H04N116

CPC分类号： H04L49/258 ,  H04J3/1611 ,  H04J2203/0023 ,  H04L49/25 ,  H04L49/552

摘要： A simple, elementary switch fabric is provided for switching individual signals as a composite group based on group signal status that is embedded and carried within each of the individual signals in the group. In general, a group signal status is derived for a group based on the signal status of each of the individual signals within that group. This group signal status is then individually encoded and embedded in each of the individual signals in the group. The embedded group signal status can be extracted and decoded at any point within the transmission path, as necessary, to facilitate appropriate switching decisions. Although each individual signal is switched independently by the elementary switch fabric, the individual signals are effectively switched as a composite group because the switching decision for each individual signal in the group is based on the same group signal status. That is, individual signals in a particular group will either be selected or rejected together as a single, composite group.

摘要翻译： 提供了简单的基本交换结构，用于基于组中的每个单独信号中嵌入和携带的组信号状态来将各个信号切换为复合组。 通常，基于该组内的各个信号的信号状态，针对组导出组信号状态。 然后将该组信号状态单独地编码并嵌入到组中的每个单独信号中。 可以根据需要在传输路径内的任何点处提取和解码嵌入式组信号状态，以便于适当的切换决策。 虽然每个单独的信号由基本交换结构独立地切换，但是由于组中每个单独信号的切换决定基于相同的组信号状态，所以各个信号被有效地切换为复合组。 也就是说，特定组中的单个信号将作为单个复合组一起被选择或拒绝。