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公开(公告)号：US10223994B2
公开(公告)日：2019-03-05
申请号：US15862185
申请日：2018-01-04
Inventor： Toshio Miyazawa , Iwao Takemoto , Atsushi Hasegawa , Masahiro Maki , Kazutaka Goto
Abstract: A display driving circuit having a shift register is formed on the display panel. The shift register includes a first stage having first and second transistors and a second stage having a third and fourth transistor. A voltage of a control electrode of the first transistor is boosted by a voltage of a first pulse line changing from low to high. In an On state, the second transistor connects the control electrode of the first transistor and a constant voltage line. A voltage of a control electrode of the third transistor is boosted by a voltage of a second pulse line changing from low to high. In an On state, the fourth transistor connects the control electrode of the third transistor and a constant voltage line. The fourth transistor is switched on by a signal from the first stage.
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公开(公告)号：US10147377B2
公开(公告)日：2018-12-04
申请号：US15808142
申请日：2017-11-09
Applicant: Japan Display Inc.
Inventor： Hiroyuki Abe , Masahiro Maki , Hiroaki Komatsu
Abstract: A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.
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公开(公告)号：US20180174539A1
公开(公告)日：2018-06-21
申请号：US15898272
申请日：2018-02-16
Applicant: Japan Display Inc.
Inventor： Takayuki SUZUKI , Hiroyuki Abe , Masahiro Maki , Mitsuru Goto
IPC: G09G3/36 , G02F1/1333 , G02F1/1335 , G02F1/1362 , G06F3/041 , G06F3/044 , G02F1/133
CPC classification number: G09G3/3655 , G02F1/13306 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133528 , G02F1/136286 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/0418 , G06F3/044 , G06F2203/04103 , G09G3/36 , G09G2300/0426 , G09G2320/0219 , G09G2320/0626
Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.
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公开(公告)号：US09865215B2
公开(公告)日：2018-01-09
申请号：US15361785
申请日：2016-11-28
Applicant: Japan Display Inc.
Inventor： Hiroyuki Abe , Masahiro Maki , Hideo Sato , Hiroaki Komatsu
CPC classification number: G09G3/3677 , G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0248 , G09G2310/0251 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0297 , G09G2310/08
Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: a gate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
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公开(公告)号：US09632378B2
公开(公告)日：2017-04-25
申请号：US13645651
申请日：2012-10-05
Applicant: Japan Display Inc.
Inventor： Hiroyuki Abe , Masahiro Maki , Tomonori Nishino
IPC: G02F1/1343 , G02F1/1362 , H01L29/786 , G02F1/1333 , H01L27/12
CPC classification number: G02F1/136286 , G02F1/136204 , G02F2001/133388 , H01L27/1214 , H01L27/1244 , H01L29/78651
Abstract: A display device includes a display area as an area having a plurality pixels each including a thin film transistor, and adapted to display an image, and a dummy pixel area formed outside the display area, and having a plurality of dummy pixels. The dummy pixel includes a dummy gate signal line parallel to a gate signal line of the thin film transistor, and a semiconductor layer intersecting with the dummy gate signal line via an insulating layer. Just one conductor layer is connected to the semiconductor layer.
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Patent Agency Ranking
公开(公告)号：US10585517B2
公开(公告)日：2020-03-10
申请号：US16437036
申请日：2019-06-11
Applicant: Japan Display Inc.
Inventor： Hiroyuki Abe , Masahiro Maki , Takayuki Suzuki
IPC: G02F1/1345 , G06F3/041 , G02F1/1333 , G06F3/044 , G02F1/1343 , G02F1/1362
Abstract: The presence or absence of touch is detected according to a difference of a capacitance caused by the presence or absence of a material that blocks the electric field formed between the detection electrode and the common electrode. The common electrode includes a plurality of divided electrode portions that is extended in a lateral direction and aligned with each other in a longitudinal direction. Each of the plurality of common lines is electrically connected to at least one of the divided electrode portions. The plurality of common lines is arranged in an area next to the common electrode in the lateral direction of the common electrode, arranged next to each other in a width direction orthogonal to a length thereof, is different in width from each other, and the width of the common lines is wider as the length is longer.
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公开(公告)号：US20180144704A1
公开(公告)日：2018-05-24
申请号：US15862185
申请日：2018-01-04
Inventor： Toshio Miyazawa , Iwao Takemoto , Atsushi Hasegawa , Masahiro Maki , Kazutaka Goto
IPC: G09G3/36 , G11C19/18 , H01L27/12 , H01L29/423 , G11C19/28
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
Abstract: A display driving circuit having a shift register is formed on the display panel. The shift register includes a first stage having first and second transistors and a second stage having a third and fourth transistor. A voltage of a control electrode of the first transistor is boosted by a voltage of a first pulse line changing from low to high. In an On state, the second transistor connects the control electrode of the first transistor and a constant voltage line. A voltage of a control electrode of the third transistor is boosted by a voltage of a second pulse line changing from low to high. In an On state, the fourth transistor connects the control electrode of the third transistor and a constant voltage line. The fourth transistor is switched on by a signal from the first stage.
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公开(公告)号：US09928792B2
公开(公告)日：2018-03-27
申请号：US15497286
申请日：2017-04-26
Applicant: Japan Display Inc.
Inventor： Takayuki Suzuki , Hiroyuki Abe , Masahiro Maki , Mitsuru Goto
IPC: G06F3/044 , G09G3/36 , G06F3/041 , G02F1/1362 , G02F1/1333 , G02F1/1335 , G02F1/133
CPC classification number: G09G3/3655 , G02F1/13306 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133528 , G02F1/136286 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/0418 , G06F3/044 , G06F2203/04103 , G09G3/36 , G09G2300/0426 , G09G2320/0219 , G09G2320/0626
Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.
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公开(公告)号：US09927900B2
公开(公告)日：2018-03-27
申请号：US15584069
申请日：2017-05-02
Applicant: Japan Display Inc.
Inventor： Hiroyuki Abe , Masahiro Maki , Takayuki Suzuki
IPC: G02F1/1362 , G06F3/041 , G06F3/044 , G02F1/1333 , G02F1/1343
CPC classification number: G06F3/0412 , G02F1/13338 , G02F1/134363 , G02F1/1345 , G02F1/136286 , G02F2001/134318 , G02F2201/121 , G06F3/0418 , G06F3/044
Abstract: The presence or absence of touch is detected according to a difference of a capacitance caused by the presence or absence of a material that blocks the electric field formed between the detection electrode and the common electrode. The common electrode includes a plurality of divided electrode portions that is extended in a lateral direction and aligned with each other in a longitudinal direction. Each of the plurality of common lines is electrically connected to at least one of the divided electrode portions. The plurality of common lines is arranged in an area next to the common electrode in the lateral direction of the common electrode, arranged next to each other in a width direction orthogonal to a length thereof, is different in width from each other, and the width of the common lines is wider as the length is longer.
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公开(公告)号：US09489879B2
公开(公告)日：2016-11-08
申请号：US14825042
申请日：2015-08-12
Applicant: Japan Display Inc.
Inventor： Hiroyuki Abe , Masahiro Maki , Hiroaki Komatsu
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/2018 , G09G3/3674 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/28
Abstract: A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.
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