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公开(公告)号：US20060039376A1
公开(公告)日：2006-02-23
申请号：US10868725
申请日：2004-06-15
CPC分类号： H04L49/90 , H04L49/9042 , H04L49/9073 , H04L69/22
摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.
摘要翻译： 提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。 网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。 芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。 该方法包括利用报头信息来识别分组的其余部分的位置和范围。 当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时 有空间。
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公开(公告)号：US20060168583A1
公开(公告)日：2006-07-27
申请号：US11042692
申请日：2005-01-25
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Harm Hofstee , Fabrice Verplanken , Colin Verrilli
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Harm Hofstee , Fabrice Verplanken , Colin Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译： 公开了用于在多线程数字处理器的流水线中分发线程指令的系统和方法。 更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。 如果要选择的线程无法执行，则选择补充线程执行。
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公开(公告)号：US20060026342A1
公开(公告)日：2006-02-02
申请号：US10899937
申请日：2004-07-27
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
摘要翻译： 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。
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4.发明申请Structure and method for scheduler pipeline design for hierarchical link sharing 失效用于分层链路共享的调度器流水线设计的结构和方法公开(公告)号：US20050177644A1
公开(公告)日：2005-08-11
申请号：US10772737
申请日：2004-02-05
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译： 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。
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公开(公告)号：US20070294471A1
公开(公告)日：2007-12-20
申请号：US11832220
申请日：2007-08-01
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
摘要翻译： 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。
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公开(公告)号：US20050022196A1
公开(公告)日：2005-01-27
申请号：US10915983
申请日：2004-08-11
申请人： Gordon Davis , Marco Heddes , Ross Leavens , Fabrice Verplanken
发明人： Gordon Davis , Marco Heddes , Ross Leavens , Fabrice Verplanken
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译： 机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。
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公开(公告)号：US20060271576A1
公开(公告)日：2006-11-30
申请号：US11462404
申请日：2006-08-04
申请人： Claude Basso , Jean Calvignac , Gordon Davis , Marco Heddes , Piyush Patel , Steven Perrin , Grayson Randall , Sonia Rovner
发明人： Claude Basso , Jean Calvignac , Gordon Davis , Marco Heddes , Piyush Patel , Steven Perrin , Grayson Randall , Sonia Rovner
IPC分类号： G06F7/00
CPC分类号： G06F17/30625 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943
摘要： A technique is provided to delete a leaf from a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as a leaf to be deleted. Using the pattern, the tree is walked to identify the location of the leaf to be deleted. The leaf to be deleted is identified and deleted, and any relevant PSCB modified, if necessary. The technique also is applicable to deleting a prefix of a prefix.
摘要翻译： 提供一种技术来从具有直接表的帕特里夏树和多个PSCB中删除叶，该PSCB解码树中的叶的图案的部分，而不关闭树的功能。 具有图案的叶被识别为要被删除的叶。 使用图案，树被移动以识别要删除的叶子的位置。 要删除的叶被识别和删除，并且必要时修改任何相关的PSCB。 该技术也适用于删除前缀的前缀。
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公开(公告)号：US20080013541A1
公开(公告)日：2008-01-17
申请号：US11776807
申请日：2007-07-12
申请人： Jean Calvignac , Gordon Davis
发明人： Jean Calvignac , Gordon Davis
IPC分类号： H04L12/54
CPC分类号： H04L49/602 , H04L49/354 , H04L49/604 , H04L69/22
摘要： A method and structure are disclosed for dispatching appropriate data to a network processing system comprising an improved technique for extracting protocol header fields for use by the network processor. This technique includes basic classification of a packet according to the types of protocol headers present in the packet. Based on the results of the classification, specific parameter fields are extracted from corresponding headers. All such parameter fields from one or more protocol headers in the packet are concatenated into a compressed dispatch message. Multiples of such dispatch messages are bundled into a single composite dispatch message. Thus, selected header fields from N packets are passed to the network processor in a single composite dispatch message, increasing the network processor's packet forwarding capacity by a factor of N. Likewise, multiple enqueue messages are bundled into a single composite enqueue message to direct enqueue and frame alterations to be taken on the bundle of N packets.
摘要翻译： 公开了一种用于将适当数据发送到网络处理系统的方法和结构，所述网络处理系统包括用于提取网络处理器使用的协议头域的改进技术。 该技术包括根据分组中存在的协议报头的类型对分组的基本分类。 根据分类结果，从相应的标题中提取特定参数字段。 来自分组中的一个或多个协议报头的所有这些参数字段被连接成压缩的调度消息。 这种分派消息的倍数被捆绑成单个复合调度消息。 因此，来自N个分组的选择的报头字段以单个复合调度消息传递到网络处理器，从而将网络处理器的分组转发能力提高N倍。同样地，多个入队消息被捆绑到单个复合入口消息中以引导入队 并且对N个分组的束进行帧改变。
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9.发明申请NETWORK PROCESSOR WITH SINGLE INTERFACE SUPPORTING TREE SEARCH ENGINE AND CAM 失效网络处理器，具有单接口支持树搜索引擎和CAM公开(公告)号：US20060265363A1
公开(公告)日：2006-11-23
申请号：US11457952
申请日：2006-07-17
申请人： Jean Calvignac , Gordon Davis , Marco Heddes , Michael Siegel
发明人： Jean Calvignac , Gordon Davis , Marco Heddes , Michael Siegel
IPC分类号： G06F17/30
CPC分类号： H04L49/3009 , G11C15/00 , H04L45/745 , H04L45/7453 , H04L49/90
摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.
摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。
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公开(公告)号：US20060173831A1
公开(公告)日：2006-08-03
申请号：US11353841
申请日：2006-02-14
申请人： Claude Basso , Jean Calvignac , Gordon Davis , Piyush Patel
发明人： Claude Basso , Jean Calvignac , Gordon Davis , Piyush Patel
IPC分类号： G06F17/30
CPC分类号： H04L45/00 , G06F17/30985 , H04L12/66 , H04L45/745 , H04L45/7457 , Y10S707/99933 , Y10S707/99935 , Y10S707/99936
摘要： A method and apparatus are used for finding the longest prefix match in a variable length prefix search when searching a direct table within a routing table structure of a network processor. The search through the routing table structure is expedited by hashing a first segment of an internet protocol address with a virtual private network number followed by concatenating the unhashed bits of the IP address to the result of the hash operation to form an input key. Patterns are compared a bit at a time until an exact match or the best match is found. The search is conducted in a search tree that provides that the matching results will be the best possible match.
摘要翻译： 当在网络处理器的路由表结构中搜索直接表时，使用方法和装置来在可变长度前缀搜索中找到最长的前缀匹配。 通过路由表结构的搜索是通过用互联网协议地址的第一段与虚拟专用网络号进行散列加速，然后将IP地址的未分配比特连接到散列操作的结果以形成输入密钥。 模式一次比较一点，直到找到完全匹配或最佳匹配。 搜索在搜索树中进行，其提供匹配结果将是最佳匹配。
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