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    HIGH k GATE STACK ON III-V COMPOUND SEMICONDUCTORS
    1.
    发明申请
    HIGH k GATE STACK ON III-V COMPOUND SEMICONDUCTORS 有权
    III-V复合半导体的高k栅极堆叠

    公开(公告)号：US20120326212A1

    公开(公告)日：2012-12-27

    申请号：US13607741

    申请日：2012-09-09

    申请人： Jean Fompeyrine ,  Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  David J. Webb

    发明人： Jean Fompeyrine ,  Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  David J. Webb

    IPC分类号： H01L29/267 ,  H01L21/20 ,  H01L21/336 ,  H01L21/324

    CPC分类号： H01L21/3205 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/28158 ,  H01L21/3145 ,  H01L21/31645 ,  H01L21/32051 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AOxNy prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.

    摘要翻译： 提供了在III-V族化合物半导体的这种GaAs的表面上形成高k栅极堆叠的方法。 该方法包括使III-V族化合物半导体材料进行从III-V族化合物半导体材料的表面除去天然氧化物的预清洗工艺; 在III-V族化合物半导体材料的清洁表面上原位形成半导体，例如非晶Si层; 以及在所述半导体层上形成介电常数大于二氧化硅的电介质材料。 在一些实施例中，半导体层在形成电介质材料之前部分地或完全地转变成包括至少由AOxNy构成的表面层的层。 根据本发明，A是半导体材料，优选Si，x为0至1，y为0至1，x和y都不为零。

    Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics
    3.
    发明授权
    Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics 有权
    使用III-V复合半导体和高k栅极电介质的掩埋沟道MOSFET

    公开(公告)号：US07964896B2

    公开(公告)日：2011-06-21

    申请号：US12180927

    申请日：2008-07-28

    申请人： Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  Ghavam Shahidi ,  Yanning Sun

    发明人： Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  Ghavam Shahidi ,  Yanning Sun

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7787 ,  H01L29/66462

    摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

    摘要翻译： 一种含半导体的异质结构，包括III-V族化合物半导体缓冲层，III-V族化合物半导体沟道层，III-V族化合物半导体阻挡层和任选的，但优选的III-V族化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 III-V族化合物半导体缓冲层和III-V族化合物半导体阻挡层由具有比III-V化合物半导体沟道层宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

    BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS
    7.
    发明申请
    BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS 有权
    使用III-V复合半导体和高k栅介质的BURIED CHANNEL MOSFET

    公开(公告)号：US20080296622A1

    公开(公告)日：2008-12-04

    申请号：US12180927

    申请日：2008-07-28

    申请人： Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  Ghavam Shahldi ,  Yanning Sun

    发明人： Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  Ghavam Shahldi ,  Yanning Sun

    IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L21/205

    CPC分类号： H01L29/7787 ,  H01L29/66462

    摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

    摘要翻译： 一种含半导体的异质结构，包括III-V族化合物半导体缓冲层，III-V族化合物半导体沟道层，III-V族化合物半导体阻挡层和任选的，但优选的III-V族化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 III-V族化合物半导体缓冲层和III-V族化合物半导体阻挡层由具有比III-V化合物半导体沟道层宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。