公开(公告)号：US08431476B2

公开(公告)日：2013-04-30

申请号：US13570980

申请日：2012-08-09

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L21/28 ,  H01L21/3205

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

公开(公告)号：US08415772B2

公开(公告)日：2013-04-09

申请号：US13570989

申请日：2012-08-09

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L23/58

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

摘要翻译： 提供了防止III-V族化合物半导体的表面分解的方法。 该方法包括在III-V族化合物半导体的表面上形成厚度为从至400的硅膜。 在III-V族化合物半导体的表面上形成硅膜之后，可以在封盖/钝化的III-V化合物半导体上形成包括例如MOSFET的高性能半导体器件。 在MOSFET制造期间，可以在封盖/钝化的III-V化合物半导体上形成高k电介质，此后可以将激活的源极和漏极区域形成为III-V族化合物半导体。

公开(公告)号：US20120309153A1

公开(公告)日：2012-12-06

申请号：US13570980

申请日：2012-08-09

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L21/336

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

公开(公告)号：US20120305989A1

公开(公告)日：2012-12-06

申请号：US13570989

申请日：2012-08-09

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L29/78

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

摘要翻译： 提供了防止III-V族化合物半导体的表面分解的方法。 该方法包括在III-V族化合物半导体的表面上形成厚度为从至400的硅膜。 在III-V族化合物半导体的表面上形成硅膜之后，可以在封盖/钝化的III-V化合物半导体上形成包括例如MOSFET的高性能半导体器件。 在MOSFET制造期间，可以在封盖/钝化的III-V化合物半导体上形成高k电介质，此后可以将激活的源极和漏极区域形成为III-V族化合物半导体。

公开(公告)号：US08273649B2

公开(公告)日：2012-09-25

申请号：US12272129

申请日：2008-11-17

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L21/28 ,  H01L21/3205

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

摘要翻译： 提供了防止III-V族化合物半导体的表面分解的方法。 该方法包括在III-V族化合物半导体的表面上形成厚度为从至400的硅膜。 在III-V族化合物半导体的表面上形成硅膜之后，可以在封盖/钝化的III-V化合物半导体上形成包括例如MOSFET的高性能半导体器件。 在MOSFET制造期间，可以在封盖/钝化的III-V化合物半导体上形成高k电介质，此后可以将激活的源极和漏极区域形成为III-V族化合物半导体。

公开(公告)号：US20100123205A1

公开(公告)日：2010-05-20

申请号：US12272129

申请日：2008-11-17

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

摘要翻译： 提供了防止III-V族化合物半导体的表面分解的方法。 该方法包括在III-V族化合物半导体的表面上形成厚度为从至400的硅膜。 在III-V族化合物半导体的表面上形成硅膜之后，可以在封盖/钝化的III-V化合物半导体上形成包括例如MOSFET的高性能半导体器件。 在MOSFET制造期间，可以在封盖/钝化的III-V化合物半导体上形成高k电介质，此后可以将激活的源极和漏极区域形成为III-V族化合物半导体。

公开(公告)号：US07365399B2

公开(公告)日：2008-04-29

申请号：US11333074

申请日：2006-01-17

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/32 ,  H01L21/0203 ,  H01L21/76259 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/78

摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

摘要翻译： 提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。 更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。 还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。 该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层 。

公开(公告)号：US07842940B2

公开(公告)日：2010-11-30

申请号：US12062164

申请日：2008-04-03

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

IPC分类号： H01L31/00

CPC分类号： H01L29/32 ,  H01L21/0203 ,  H01L21/76259 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/78

摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

摘要翻译： 提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。 更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。 还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。 该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层 。

公开(公告)号：US20090134460A1

公开(公告)日：2009-05-28

申请号：US12363239

申请日：2009-01-30

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/00 ,  H01L21/71

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

公开(公告)号：US07485539B2

公开(公告)日：2009-02-03

申请号：US11332564

申请日：2006-01-13

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/76

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。