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    Doped structures containing diffusion barriers
    2.
    发明授权
    Doped structures containing diffusion barriers 失效
    含有扩散阻挡层的掺杂结构

    公开(公告)号：US06399434B1

    公开(公告)日：2002-06-04

    申请号：US09559880

    申请日：2000-04-26

    Applicant: Susan E. Chaloux ,  Johnathan E. Faltermeier ,  Ulrike Gruening ,  Rajarao Jammy ,  Christopher C. Parks ,  Paul Parries ,  Paul A. Ronsheim ,  Jean-Marc Rousseau

    Inventor： Susan E. Chaloux ,  Johnathan E. Faltermeier ,  Ulrike Gruening ,  Rajarao Jammy ,  Christopher C. Parks ,  Paul Parries ,  Paul A. Ronsheim ,  Jean-Marc Rousseau

    IPC: H01L218242

    CPC classification number: H01L27/10867 ,  H01L21/28512

    Abstract: Semiconductor structures having improved dopant configurations are obtained by use of barrier layers containing silicon, nitrogen, and oxygen atoms and having a thickness of about 5 to 50 Å. A doped semiconductor structure with controlled dopant configuration can be formed by: (a) providing a first semiconductor material region, (b) forming an interface layer comprising silicon, oxygen, and nitrogen on the first region, (c) forming a second semiconductor material region on the interface layer, the second semiconductor material region being on an opposite side of the interface layer from the first semiconductor material region, (d) providing a dopant in the second region, and (e) heating the first and second regions whereby at least a portion of the dopant diffuses from the second region through the interface layer to the first region.

    Abstract translation: 具有改进的掺杂剂构型的半导体结构通过使用包含硅，氮和氧原子并且具有约5至约50埃的厚度的阻挡层来获得。 具有受控掺杂剂配置的掺杂半导体结构可以通过以下方式形成：（a）提供第一半导体材料区域，（b）在第一区域上形成包含硅，氧和氮的界面层，（c）形成第二半导体材料 区域，所述第二半导体材料区域在与所述第一半导体材料区域的所述界面层的相对侧上，（d）在所述第二区域中提供掺杂剂，以及（e）加热所述第一区域和所述第二区域， 掺杂剂的至少一部分从第二区域扩散通过界面层到第一区域。

    Method of forming a dopant outdiffusion control structure including selectively grown silicon nitride in a trench capacitor of a DRAM cell
    3.
    发明授权
    Method of forming a dopant outdiffusion control structure including selectively grown silicon nitride in a trench capacitor of a DRAM cell 失效
    在DRAM单元的沟槽电容器中形成包括选择性地生长的氮化硅的掺杂剂扩散扩散控制结构的方法

    公开(公告)号：US5998253A

    公开(公告)日：1999-12-07

    申请号：US993743

    申请日：1997-12-19

    Applicant: Stephen K. Loh ,  Christine Dehm ,  Christopher C. Parks

    Inventor： Stephen K. Loh ,  Christine Dehm ,  Christopher C. Parks

    IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/49 ,  H01L21/70

    CPC classification number: H01L21/8238 ,  H01L21/28061 ,  H01L29/4916 ,  H01L29/4933

    Abstract: A method for controlling dopant outdiffusion within an integrated circuit is disclosed. The method includes providing a substrate, forming a trench in the substrate, and forming a first doped layer in the trench. The first doped layer has a first dopant concentration. The method further includes forming a dopant diffusion control structure above the first doped layer. The dopant diffusion control structure includes silicon nitride (Si.sub.x N.sub.y) disposed in grain boundaries of the first doped layer. The method also includes forming a second layer above the dopant diffusion control structure. The second layer has a second dopant concentration lower than the first dopant concentration. Forming the dopant diffusion control structure includes, in one example, forming a first oxide layer over the first doped silicon layer, nitridizing the first oxide layer, thereby forming an oxynitride (SiO.sub.x N.sub.y) layer and causing the silicon nitride to migrate into the grain boundaries, and removing the oxynitride layer, thereby exposing the silicon nitride at the grain boundaries at an interface of the first doped layer.

    Abstract translation: 公开了一种用于控制集成电路内的掺杂物扩散扩散的方法。 该方法包括提供衬底，在衬底中形成沟槽，以及在沟槽中形成第一掺杂层。 第一掺杂层具有第一掺杂浓度。 该方法还包括在第一掺杂层之上形成掺杂剂扩散控制结构。 掺杂剂扩散控制结构包括设置在第一掺杂层的晶界中的氮化硅（SixNy）。 该方法还包括在掺杂剂扩散控制结构上方形成第二层。 第二层具有低于第一掺杂剂浓度的第二掺杂剂浓度。 在一个示例中，形成掺杂剂扩散控制结构包括在第一掺杂硅层上形成第一氧化物层，对第一氧化物层进行氮化，从而形成氧氮化物（SiO x N y）层并使氮化硅迁移到晶界， 并去除氧氮化物层，从而在第一掺杂层的界面处的晶界暴露氮化硅。

    Gas treatment of thin film structures with catalytic action
    8.
    发明授权
    Gas treatment of thin film structures with catalytic action 失效
    具有催化作用的薄膜结构气体处理

    公开(公告)号：US06815343B2

    公开(公告)日：2004-11-09

    申请号：US10334178

    申请日：2002-12-30

    Applicant: John D. Baniecki ,  Robert B. Laibowitz ,  Christopher C. Parks ,  Thomas M. Shaw

    Inventor： John D. Baniecki ,  Robert B. Laibowitz ,  Christopher C. Parks ,  Thomas M. Shaw

    IPC: H01L2144

    CPC classification number: H01L21/3003 ,  H01L21/28185 ,  H01L21/324 ,  H01L29/513

    Abstract: A method of substantially reducing and/or eliminating the amount of defects and/or impurities that amass at interfacial surfaces that are present in a multilayer structure is provided. Specifically, the method improves the efficiency of a forming gas anneal by providing a multilayer structure having a catalytic layer formed thereon or buried therein which allows for a significant increase in the amount of hydrogen or deuterium which can be incorporated into the structure. The method is also conducted at a low temperature (on the order of about 400° C. or less). Multilayer structures are also provided which include an annealed multilayer structure having at least one interfacial surface present therein. The at least one material interface contains a region of hydrogen or deuterium which substantially reduces defects and impurities present at the at least one interface.

    Clean method for recessed conductive barriers
    9.
    发明授权
    Clean method for recessed conductive barriers 有权
    凹陷导电屏障的清洁方法

    公开(公告)号：US06358855B1

    公开(公告)日：2002-03-19

    申请号：US09595795

    申请日：2000-06-16

    Applicant: Ravikumar Ramachandran ,  Nicolas Nagel ,  Christopher C. Parks

    Inventor： Ravikumar Ramachandran ,  Nicolas Nagel ,  Christopher C. Parks

    IPC: H01L21302

    CPC classification number: H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76861 ,  H01L21/7687 ,  H01L27/10855

    Abstract: A method for cleaning an oxidized diffusion barrier layer, in accordance with the present invention, includes providing a conductive diffusion barrier layer employed for preventing oxygen and metal diffusion therethrough and providing a wet chemical etchant including hydrofluoric acid. The diffusion barrier layer is etched with the wet chemical etchant to remove oxides from the diffusion barrier layer such that by employing the wet chemical etchant linear electrical behavior is achieved through the diffusion barrier layer.

    Abstract translation: 根据本发明的用于清洁氧化扩散阻挡层的方法包括提供用于防止氧和金属扩散的导电扩散阻挡层，并提供包括氢氟酸在内的湿化学蚀刻剂。 用湿化学蚀刻剂蚀刻扩散阻挡层以从扩散阻挡层去除氧化物，使得通过使用湿化学蚀刻剂，通过扩散阻挡层实现线性电性能。

    Method for forming field effect transistors having different threshold voltages and devices formed thereby
    10.
    发明授权
    Method for forming field effect transistors having different threshold voltages and devices formed thereby 失效
    用于形成具有不同阈值电压的场效应晶体管的方法和由此形成的器件

    公开(公告)号：US5907777A

    公开(公告)日：1999-05-25

    申请号：US903671

    申请日：1997-07-31

    Applicant: Thomas W. Joseph ,  Christopher C. Parks

    Inventor： Thomas W. Joseph ,  Christopher C. Parks

    IPC: H01L21/8234

    CPC classification number: H01L21/823462

    Abstract: The preferred embodiment provides a method for fabricating field effect transistors that have different threshold voltages without requiring excessive masking and other fabrication steps. In particular, the method facilitates the formation of FETs with different threshold voltages by doping the gate dielectric with various amounts of ions. This provides a built in potential in the gate dielectric proportional to the amount of ions in the gate dielectric. This potential changes the threshold voltage of the FET. Thus, by selectively doping the gate dielectric with ions the threshold voltage of a FET can be changed. The selective doping of many FETs to many different threshold voltages can be done with only one additional masking step. Thus, the present invention provides the ability to form FETs having different threshold voltages without requiring excessive process complexity.

    Abstract translation: 优选实施例提供了一种用于制造具有不同阈值电压而不需要过度掩蔽和其它制造步骤的场效应晶体管的方法。 特别地，该方法通过用不同量的离子掺杂栅极电介质来促进形成具有不同阈值电压的FET。 这提供了栅极电介质中的内置电位，与栅极电介质中的离子量成比例。 该电位改变FET的阈值电压。 因此，通过用离子选择性地掺杂栅极电介质，可以改变FET的阈值电压。 许多FET的许多不同阈值电压的选择性掺杂可以仅用一个附加的掩模步骤来完成。 因此，本发明提供了形成具有不同阈值电压的FET的能力，而不需要过多的工艺复杂性。

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