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1.发明授权公开(公告)号：US06277661B1
公开(公告)日：2001-08-21
申请号：US09677955
申请日：2000-10-02
申请人： Jean Yang , Ian Dudley , Khoi Phan
发明人： Jean Yang , Ian Dudley , Khoi Phan
IPC分类号： H01L2166
摘要： A method for contact hole formation and inspection during integrated circuit fabrication is disclosed. The method includes defining tolerances for one or more contact hole formation processes, and then performing the formation processes to create at least one contact hole. After at least one of the formation processes is performed, a waveform is generated for the contact hole. A critical dimension (CD) and an edge width value are then generated for the contact hole from the waveform. The CD and the edge width value are then compared to the tolerances to detect and correct variations in the formation process. In a further aspect of the present invention, the edge width is compared to a predetermined limit to automatically detect contact holes having sloped sidewalls.
摘要翻译： 公开了一种在集成电路制造期间接触孔形成和检查的方法。 该方法包括确定一个或多个接触孔形成过程的公差，然后执行形成过程以产生至少一个接触孔。 在执行至少一个形成处理之后，产生用于接触孔的波形。 然后为波形的接触孔产生临界尺寸（CD）和边缘宽度值。 然后将CD和边缘宽度值与公差进行比较，以检测和纠正形成过程中的变化。 在本发明的另一方面，将边缘宽度与预定极限进行比较，以自动检测具有倾斜侧壁的接触孔。
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公开(公告)号：US06441398B2
公开(公告)日：2002-08-27
申请号：US09894670
申请日：2001-06-27
申请人： Jean Yang , Ian Dudley , Khoi Phan
发明人： Jean Yang , Ian Dudley , Khoi Phan
IPC分类号： H01L2358
摘要： A method for contact hole formation and inspection during integrated circuit fabrication is disclosed. The method includes defining tolerances for one or more contact hole formation processes, and then performing the formation processes to create at least one contact hole. After at least one of the formation processes is performed, a waveform is generated for the contact hole. A critical dimension (CD) and an edge width value are then generated for the contact hole from the waveform. The CD and the edge width value are then compared to the tolerances to detect and correct variations in the formation process. In a further aspect of the present invention, the edge width is compared to a predetermined limit to automatically detect contact holes having sloped sidewalls.
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3.发明授权System and method for constructing a profile of a structure in an integrated circuit 失效用于构建集成电路中的结构的轮廓的系统和方法公开(公告)号：US06627887B1
公开(公告)日：2003-09-30
申请号：US09597187
申请日：2000-06-20
申请人： Ian Dudley , Jean Yang , Paula Rao
发明人： Ian Dudley , Jean Yang , Paula Rao
IPC分类号： G01N2300
CPC分类号： G01N23/2251
摘要： A system and method are provided for profiling a structure in an integrated circuit to determine the structural dimensions. The system comprises a processor circuit that includes a processor electrically coupled to a local interface and a memory electrically coupled to the local interface, where the local interface comprises, for example, a data bus and associated control bus. The system further comprises a critical dimension scanning electron microscope having a signal output electrically coupled to the local interface and operating logic stored on the memory and executable by the processor. The operating logic comprises logic to execute a scan of a structure in an integrated circuit using the SEM, logic to store a first derivative waveform generated from the scan in the memory, and logic to generate a profile of the structure from the first derivative waveform.
摘要翻译： 提供了一种用于对集成电路中的结构进行分析以确定结构尺寸的系统和方法。 该系统包括处理器电路，其包括电耦合到本地接口的处理器和电耦合到本地接口的存储器，其中本地接口包括例如数据总线和相关联的控制总线。 该系统还包括具有电耦合到本地接口的信号输出和存储在存储器上并由处理器执行的操作逻辑的临界尺寸扫描电子显微镜。 操作逻辑包括使用SEM执行集成电路中的结构的扫描的逻辑，用于存储从存储器中的扫描产生的一阶微分波形的逻辑，以及从一阶导数波形生成结构的曲线的逻辑。
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公开(公告)号：US07432178B2
公开(公告)日：2008-10-07
申请号：US11254769
申请日：2005-10-21
申请人： Angela T. Hui , Jean Yang , Yu Sun , Mark T. Ramsbey , Weidong Qian
发明人： Angela T. Hui , Jean Yang , Yu Sun , Mark T. Ramsbey , Weidong Qian
IPC分类号： H01L21/04
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.
摘要翻译： 公开了一种用于执行位线植入的方法。 该方法包括在半导体器件的氧化物 - 氮化物 - 氧化物堆叠上形成一组结构。 该组结构的每个结构包括多晶硅部分和硬掩模部分。 该组结构的第一结构与该组结构的第二结构分开小于100纳米。 该方法还包括使用第一结构和第二结构来隔离位线植入物的半导体器件的一部分。
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公开(公告)号：US07998846B2
公开(公告)日：2011-08-16
申请号：US12209478
申请日：2008-09-12
申请人： Eunha Kim , Jeremy Wahl , Shenqing Fang , YouSeok Suh , Kuo-Tung Chang , Yi Ma , Rinji Sugino , Jean Yang
发明人： Eunha Kim , Jeremy Wahl , Shenqing Fang , YouSeok Suh , Kuo-Tung Chang , Yi Ma , Rinji Sugino , Jean Yang
IPC分类号： H01L21/263
CPC分类号： H01L21/02675 , H01L21/02592 , H01L21/02691
摘要： A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.
摘要翻译： 提出了半导体制造系统和方法。 三维多层集成电路制造方法可以包括通过利用受控激光层形成退火工艺形成第一器件层并在第一器件层顶部形成第二器件层，并以最小的有害热传递到第一层。 可以利用受控激光结晶过程，并且受控激光器可以包括产生非晶层; 限定非晶层中的结晶区域，其中结晶区域被限定为促进单晶生长（即防止多晶生长）; 以及将激光施加到结晶区域，其中以防止不希望的热传递到另一层的方式施加激光。
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公开(公告)号：US07307027B1
公开(公告)日：2007-12-11
申请号：US11201378
申请日：2005-08-11
申请人： Minh Van Ngo , Alexander Nickel , Hieu Pham , Jean Yang , Hirokazu Tokuno , Weidong Qian
发明人： Minh Van Ngo , Alexander Nickel , Hieu Pham , Jean Yang , Hirokazu Tokuno , Weidong Qian
IPC分类号： H01L21/31
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02274 , H01L21/02304 , H01L21/76837 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of the gap between each of the multiple memory cells with a dielectric material.
摘要翻译： 在器件中的存储器单元之间形成电介质的方法包括形成多个存储器单元，其中在多个存储器单元中的每一个之间形成间隙。 该方法还包括执行高密度等离子体沉积（HDP）工艺以用电介质材料填充每个多个存储器单元之间的间隙的至少一部分。
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公开(公告)号：US07696094B2
公开(公告)日：2010-04-13
申请号：US11616563
申请日：2006-12-27
申请人： David Matsumoto , Michael Brennan , Vidyut Gopal , Jean Yang
发明人： David Matsumoto , Michael Brennan , Vidyut Gopal , Jean Yang
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A method for forming a semiconductor device may include forming a silicon oxynitride mask layer over a first layer. The first layer may be etched using the silicon oxynitride mask layer, to form a pattern in the first layer. The pattern may be filled with a dielectric material. The dielectric material may be planarized using a ceria-based slurry and using the silicon oxynitride mask layer as a stop layer.
摘要翻译： 形成半导体器件的方法可以包括在第一层上形成氮氧化硅掩模层。 可以使用氮氧化硅掩模层来蚀刻第一层，以在第一层中形成图案。 图案可以用电介质材料填充。 介电材料可以使用二氧化铈基浆料并使用氧氮化硅掩模层作为停止层进行平面化。
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