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公开(公告)号：US5471581A
公开(公告)日：1995-11-28
申请号：US146770
申请日：1993-06-23
CPC分类号： G06F5/16 , G06F13/4059 , G06F2205/063
摘要： An elastic buffer is provided between two busses working with independent clocking. The buffer is implemented by a piece of RAM memory (37) partitioned into sectors (41), each of which contains successive memory addresses. Each sector (41), can be alternatively written and read, so that at a given moment, a sector in write mode and a sector in read mode may coexist. Each sector is controlled by a mark flag (MF), a set flag corresponding to a fully written sector, and a reset flag corresponding to a sector that has been read onto the destination bus. The mark flag of each sector is set, respectively reset, upon the event of a move in pointer, respectively move out pointer, reaching the next adjacent sector. For a given elastic buffer size, the size of the sectors (41) and the number of mark flags are adaptable to the specifications of the data flow between the origin and destination busses.
摘要翻译： 两台总线之间设有一个弹性缓冲器，可以独立运行。 缓冲器由划分成扇区（41）的一块RAM存储器（37）来实现，每个扇区（41）包含连续的存储器地址。 可以替代地写入和读取每个扇区（41），使得在给定时刻，写入模式中的扇区和读取模式中的扇区可以共存。 每个扇区由标记标志（MF），对应于完全写入的扇区的设置标志以及对应于已经读取到目的地总线上的扇区的复位标志来控制。 每个扇区的标记标志分别在指针移动的情况下分别复位，分别移出指针，到达下一个相邻扇区。 对于给定的弹性缓冲器大小，扇区（41）的大小和标记标志的数量适用于原始和目的地总线之间的数据流的规范。
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2.发明授权Interface for independently establishing a link and transmitting high level commands including logical addresses from dedicated microprocessor to shared intelligent memory 失效接口独立建立链接并发送高级别命令，包括从专用微处理器到共享的智能存储器的逻辑地址
公开(公告)号：US5148527A
公开(公告)日：1992-09-15
申请号：US440569
申请日：1989-11-22
IPC分类号： G06F15/16 , G06F9/46 , G06F12/06 , G06F13/16 , G06F15/167 , G06F15/177
CPC分类号： G06F9/544 , G06F13/1652 , G06F13/1663 , G06F9/546
摘要： In a shared memory system, wherein several memory users MU wish access to a plurality of memory banks, a set of high level commands (CREATE, PUT, GET, RELEASE) is provided, to transfer data between a given memory user and the memory banks or another memory user. The high level commands sent by the memory users are built up by memory interfaces MI connected to the memory users, and transmitted through an interconnection network to Packet Memory Command Executors PMCE integrated into each memory bank. The high level commands work with data records identified by Logical Record Addresses (LRA) known by the memory users. During execution of the high level commands by the PMCE, the LRA are translated into physical addresses corresponding to physical address space in the memory banks. The physical address space is created dynamically and released upon need, through the Create or Release Commands.A given memory user is not involved at all by management of physical address space, and works only with the LRA of a record.
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3.发明授权Arbitration device for latching only the highest priority request when the common resource is busy 失效仲裁设备，用于在公共资源繁忙时仅锁存最高优先级的请求
公开(公告)号：US4752872A
公开(公告)日：1988-06-21
申请号：US745549
申请日：1985-06-17
申请人： Daniel Ballatore , Simon Huon , Jean-Marie Munier
发明人： Daniel Ballatore , Simon Huon , Jean-Marie Munier
IPC分类号： G06F13/368 , G06F13/378 , G06F13/18
CPC分类号： G06F13/378
摘要： An arbitration device for enabling a common resource to be shared by a plurality of processors, all connected by a common bus and each processor having a certain access priority. When more than one processor requests access to the resource, the highest priority processor request signal is latched and access is granted while the other requesting processor's latches remain set (access not granted). If two processors request access while the resource is busy, then only the latch of the processor having the highest priority of the two will be reset when the bus becomes available, and that processor will gain access.
摘要翻译： 一种仲裁装置，用于使公共资源由多个处理器共享，所述多个处理器全部由公共总线连接，每个处理器具有一定的访问优先级。 当多于一个处理器请求访问资源时，最高优先级处理器请求信号被锁存，并且允许访问，而另一个请求处理器的锁存器保持置位（访问未被授权）。 如果两个处理器在资源占用时请求访问，则当总线变为可用时，只有具有最高优先级的处理器的锁存器将被复位，并且该处理器将被访问。
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4.发明授权公开(公告)号：US06188698B1
公开(公告)日：2001-02-13
申请号：US09013701
申请日：1998-01-26
申请人： Claude Galand , Jean-Marie Munier , Victor Spagnol , Pierre-Andre Foriel , Jean-Marc Berthaud , Aline Fichou , Marcus Enger
发明人： Claude Galand , Jean-Marie Munier , Victor Spagnol , Pierre-Andre Foriel , Jean-Marc Berthaud , Aline Fichou , Marcus Enger
IPC分类号： G01R3108
CPC分类号： H04L47/2433 , H04L47/10 , H04L47/20 , H04L47/29 , H04L47/50 , H04L47/522 , H04L47/60 , H04L47/6225 , H04L47/625 , H04L49/3081 , H04L2012/5651 , H04L2012/5679 , H04Q11/0478
摘要： A packet scheduling system for use in a switching node of a high speed packet switching network. Incoming packets are enqueued in connection queues. Each connection is classified as red (exceeding traffic profile) or green (within traffic profile). QOS priority is also identified for each connection. Packets are dequeued for transmission as a function of priority class and connection class. Higher priority class connections have priority over lower priority class connections. Within a given priority class of connections, green connections have priority over red connections. Round robin scheduling is used for packets from connections in the same priority and connection class. In addition, a dynamic priority coupling mechanism is provided to prevent red higher priority traffic from blocking green lower priority traffic.
摘要翻译： 一种用于高速分组交换网络的交换节点的分组调度系统。 接入数据包在连接队列中排队。 每个连接分为红色（超过流量模式）或绿色（在流量模式中）。 每个连接也确定了QOS优先级。 作为优先级类和连接类的函数，数据包出队进行传输。 较高优先级的类连接优先于较低优先级的类连接。 在给定的优先级连接中，绿色连接优先于红色连接。 循环调度用于来自同一优先级和连接类的连接的数据包。 另外，提供了动态优先级耦合机制，以防止红色较高优先级的流量阻止绿色低优先级流量。
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5.发明授权
公开(公告)号：US5572697A
公开(公告)日：1996-11-05
申请号：US992314
申请日：1992-12-21
IPC分类号： G06F11/00 , G06F5/06 , G06F13/00 , G06F15/167
CPC分类号： G06F15/167 , G06F5/06 , G06F2205/064
摘要： Apparatus for recovering lost buffer contents in a data processing system uses a memory divided into a plurality of buffers provided with buffer control blocks, through which source and destination users exchange information. A buffer management circuit is responsive to requests from users for allocating buffers to source users in order that source users may store the information to be sent to the destination users. This circuit builds buffer queues and dequeues buffers from the queues to send the information contained therein to the destination users and releases the buffers afterwards. A time mark register is settable to n different values in a predetermined order. The value of the time mark register is changed at the expiration of a time period P. Each time a buffer is allocated to one user, the current value of the time mark register is written into a time mark field of the buffer control block and a state field is set to a first value (leased). When the buffer is released, the state field is set to a second value (released). The contents of the buffer control blocks are read at regular time intervals t after period P, and the state field of every buffer control block is tested to determine whether it is set to the second value. If not so set, the time mark field is compared with the value the time mark register had at the time t-xP, where x is a number such as 1
摘要翻译： 用于恢复数据处理系统中的丢失缓冲器内容的装置使用分配有缓冲器控制块的多个缓冲器的存储器，源和目的地用户通过该缓冲器控制块交换信息。 缓冲器管理电路响应于用户向源用户分配缓冲区的请求，以便源用户可以存储要发送到目的地用户的信息。 此电路构建缓冲区队列，并从队列中将缓冲区从队列中出发，将其中包含的信息发送到目标用户，然后释放缓冲区。 时间标记寄存器可按预定顺序设置为n个不同的值。 时间标记寄存器的值在时间段P的期满时被改变。每当向一个用户分配缓冲器时，时间标记寄存器的当前值被写入缓冲器控制块的时间标记字段，并且 状态字段设置为第一个值（租用）。 当释放缓冲区时，状态字段被设置为第二个值（已释放）。 在周期P之后以规则的时间间隔t读取缓冲器控制块的内容，并且测试每个缓冲器控制块的状态字段以确定其是否被设置为第二值。 如果不设置，则时间标记字段与时间标记寄存器在时间t-xP处具有的值进行比较，其中x是诸如1
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6.发明授权Low cost searching method and apparatus for asynchronous transfer mode systems 失效用于异步传输模式系统的低成本搜索方法和装置
公开(公告)号：US6097725A
公开(公告)日：2000-08-01
申请号：US61370
申请日：1998-04-16
申请人： Rene Glaise , Jean-Marie Munier
发明人： Rene Glaise , Jean-Marie Munier
CPC分类号： H04L12/5601 , H04L2012/5685
摘要： A method and an apparatus for searching a bit field whose significant bits comprise two contiguous bit fields such as the VPI/VCI bit fields of an ATM cell header. The invention uses a hash key based on CRC-n calculated on the bit field to be searched. One m bit field part of the significant bits of the bit field to be searched can be concatenated with the CRC-n to form a double hash key. It appears that, L being the total of the two contiguous bit field lengths, if L=m=n+p, p being greater or equal to 4, the scattering of data to be searched is perfect. The method comprised a first step of pointing to a first address with the hash (or double hash) key and reading a maximum of 2.sup.p addresses before reaching the addresses containing the bit field to be searched.
摘要翻译： 一种用于搜索其有效位包括诸如ATM信元头部的VPI / VCI位字段的两个连续位字段的位字段的方法和装置。 本发明使用基于要搜索的位字段上计算的CRC-n的散列密钥。 要搜索的位字段的有效位的一个m位字段部分可以与CRC-n连接以形成双散列密钥。 看来，L是两个相邻位域长度的总和，如果L = m = n + p，p大于或等于4，则要搜索的数据的散射是完美的。 该方法包括在到达包含要搜索的位字段的地址之前，使用散列（或双散列）键指向第一地址并读取最多2p地址的第一步骤。
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7.发明授权Mechanism for transferring messages between source and destination users through a shared memory 失效通过共享内存在源和目标用户之间传输消息的机制
公开(公告)号：US5333269A
公开(公告)日：1994-07-26
申请号：US965554
申请日：1992-10-23
IPC分类号： G06F15/16 , G06F13/38 , G06F13/42 , G06F15/167 , G06F15/177 , H04L12/40
CPC分类号： G06F15/167 , G06F9/544
摘要： A device for interconnecting source users and destination users includes a common bus to which a memory with a plurality of independent buffers, a memory interface (22) and a central control apparatus (26) are connected. The memory interface (22) receives messages from source users, stores the messages in selected buffers and chains the buffers together. The central control apparatus generates inbound message queues and outbound message queues in response to commands which it receives from the memory interface.
摘要翻译： 用于互连源用户和目的用户的设备包括公共总线，具有多个独立缓冲器的存储器，存储器接口（22）和中央控制设备（26）连接到该总线。 存储器接口（22）从源用户接收消息，将消息存储在所选择的缓冲器中并将缓冲器链接在一起。 中央控制装置响应于从存储器接口接收到的命令，生成入站消息队列和出站消息队列。
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8.发明授权Protocol and apparatus for a control link between a control unit and several devices 失效用于控制单元和多个设备之间的控制链路的协议和设备
公开(公告)号：US5128666A
公开(公告)日：1992-07-07
申请号：US573108
申请日：1990-02-20
IPC分类号： G06F13/42
CPC分类号： G06F13/423
摘要： An interface and protocol for linking devices (18) with a control unit (10). The interface includes a dedicated request line (30) per device, a dot-ORed acknowledge line (32), at least one clock line (38) transmitting sets of N clock pulses from the control unit to a device during each data exchange, two data line (34, 36) for serial duplex data transmission and a pair of shift registers one being positioned in the control unit and another being positioned in each of the devices. The protocol is such that for either a read or a write operation the control unit issues two request signals in spaced relationship on the request line and the selected device responds with two acknowledge signals is spaced relationship on the acknowledge line with each one of the acknowledge signals falling after the fall of its associated request signal.
摘要翻译： 一种用于将设备（18）与控制单元（10）相链接的接口和协议。 接口包括每个设备的专用请求线（30），点对应确认线（32），在每个数据交换期间至少一个时钟线（38），其将来自控制单元的N个时钟脉冲的集合发送到设备，两个 用于串行双工数据传输的数据线（34,36）和一对移位寄存器，一个位于控制单元中，另一个位于每个设备中。 该协议使得对于读取或写入操作，控制单元在请求线上以间隔的关系发出两个请求信号，并且所选择的设备以两个确认信号作出响应，在确认线上与每个确认信号 在相关联的请求信号的下降之后下降。
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公开(公告)号：US4972345A
公开(公告)日：1990-11-20
申请号：US294456
申请日：1989-01-09
CPC分类号： G06F11/0772 , G06F11/0745 , G06F13/4027 , G06F13/405
摘要： An error detection apparatus is implemented in a passive device inserted on a synchronous bus, linking two devices. The bus has data lines onto which data are transferred between the two devices under control of tag lines and clock signals which are companion of the transferred data. The apparatus allows errors to be detected, the failing device to be identified and the error signals to be reported in a psuedo-synchronous way on an error bus due to error detection and reporting logic circuits and a pseudo-synchronous timing circuit.
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10.发明授权
公开(公告)号：US4539678A
公开(公告)日：1985-09-03
申请号：US563494
申请日：1983-12-20
申请人： Modeste Ambroise , Michel Demange , Gerald Lebizay , Jean-Marie Munier , Michel H. P. Peyronnenc
发明人： Modeste Ambroise , Michel Demange , Gerald Lebizay , Jean-Marie Munier , Michel H. P. Peyronnenc
CPC分类号： H04J3/0629 , H04J3/0626 , H04L12/422 , H04Q11/04
摘要： The contents of input time-division channels on a closed-loop link (10LO, 10HI) are stored in a memory (173) at the address supplied by an input address counter (IAC) controlled by an incoming timing signal (2MCR). The memory is read out under control of an output address counter (OAC) controlled by an outgoing timing signal (2MCT). Each time interval is divided into one read period and two write periods. Means (186) are provided to select one of the two write periods dependent on the phase relationship between the incoming and outgoing timing signals. The units connected in series by means of the closed-loop link receive a timing signal circulating on a timing loop (15) that is closed by a master timing device (13). Slave timing devices (18) inserted in the timing loop regenerate the timing signals circulating thereon and check same.
摘要翻译： 在由输入定时信号（2MCR）控制的输入地址计数器（IAC）提供的地址处，存储器（173）中将闭环链路（10LO，10HI）上的输入时分信道的内容存储在存储器（173）中。 在由输出定时信号（2MCT）控制的输出地址计数器（OAC）的控制下读出存储器。 每个时间间隔分为一个读周期和两个写周期。 提供装置（186）以根据输入和输出定时信号之间的相位关系选择两个写入周期中的一个。 通过闭环链路串联连接的单元接收在由主定时装置（13）关闭的定时回路（15）上循环的定时信号。 插入定时环路的从动定时装置（18）重新产生在其上循环的定时信号并进行检查。
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