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公开(公告)号：US20130326459A1
公开(公告)日：2013-12-05
申请号：US13749851
申请日：2013-01-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31721 , G06F17/5031
摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.
摘要翻译： 一种优化集成电路（IC）芯片的功率和定时的方法，识别允许根据集成电路芯片设计产生的集成电路芯片在平均功耗目标和时序延迟目标内工作的多个有效的温度和电压组合。 这种方法从每个集成电路芯片的有效温度和电压组合中选择温度切割点，计算每个温度切断点的功率消耗量，并且基于功耗量调节温度切断点直到温度 切点实现了平均功耗目标。 接下来，该方法测试每个集成电路芯片，并将温度切割点记录在集成电路芯片的存储器中。
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公开(公告)号：US08839170B2
公开(公告)日：2014-09-16
申请号：US13749851
申请日：2013-01-25
IPC分类号： G06F17/50 , G01R31/317
CPC分类号： G06F17/5045 , G01R31/31721 , G06F17/5031
摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.
摘要翻译： 一种优化集成电路（IC）芯片的功率和定时的方法，识别允许根据集成电路芯片设计产生的集成电路芯片在平均功耗目标和时序延迟目标内工作的多个有效的温度和电压组合。 这种方法从每个集成电路芯片的有效温度和电压组合中选择温度切割点，计算每个温度切断点的功率消耗量，并且基于功耗量调节温度切断点直到温度 切点实现了平均功耗目标。 接下来，该方法测试每个集成电路芯片，并将温度切割点记录在集成电路芯片的存储器中。
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3.发明授权Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures 失效通过各种温度范围内的电压修改对集成电路进行功率和时序优化公开(公告)号：US08543960B1
公开(公告)日：2013-09-24
申请号：US13484451
申请日：2012-05-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/3004 , G01R31/3016 , G01R31/31725 , G06F17/5031
摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance.
摘要翻译： 一种通过修改提供给IC芯片的电压同时满足较低和较高温度范围内的功率消耗和定时延迟性能来优化集成电路（IC）芯片的功率和定时的方法，该集成电路（IC）芯片使用显示温度反转的IC技术 。 选择高电压，以满足整个温度范围内的闭合时序分析，以满足定时性能，并选择低电压以满足更高温度下的温度下降温度范围内的定时性能和功率性能 范围。 IC芯片在高电压下导通，并且当超过温度切断点时将高电压降低到低电压以满足功率性能同时保持定时性能。
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公开(公告)号：US09152168B2
公开(公告)日：2015-10-06
申请号：US13605050
申请日：2012-09-06
摘要： Methods and systems for system power estimation are provided. A method implemented in a computer infrastructure includes separating products into different segments. The method also includes calculating a power estimation for each segment based on operating conditions of each respective segment. The method further includes calculating an average system power estimation. At least one of the separating, calculating the power estimation, and calculating the average system power estimation is performed using a processor.
摘要翻译： 提供了系统功率估计的方法和系统。 在计算机基础设施中实现的方法包括将产品分成不同的段。 该方法还包括基于每个相应段的操作条件来计算每个段的功率估计。 该方法还包括计算平均系统功率估计。 使用处理器执行分离，计算功率估计和计算平均系统功率估计中的至少一个。
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公开(公告)号：US20130113514A1
公开(公告)日：2013-05-09
申请号：US13288269
申请日：2011-11-03
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非易失性存储介质存储电压仓的边界作为速度分级测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。
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公开(公告)号：US08421495B1
公开(公告)日：2013-04-16
申请号：US13288269
申请日：2011-11-03
IPC分类号： H03K19/003
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非易失性存储介质存储电压仓的边界作为速度分级测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。
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7.发明授权公开(公告)号：US07475366B2
公开(公告)日：2009-01-06
申请号：US11462508
申请日：2006-08-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed are embodiments of a method of designing and producing an integrated circuit. During the pre-release chip design process, the method subdivides the overall process window for an integrated circuit design into smaller successive intervals corresponding to achievable performance. Each performance interval is independently optimized for performance versus power by assigning to each interval a different corresponding supply voltage. Timing for the design is then closed for each interval at each assigned voltage. After chip manufacturing, the method measures the performance of the integrated circuits that are manufactured according to the design. Using these performance measurements, the circuits are sorted into bins corresponding to each performance interval and appropriately labeled (e.g., with the performance goal and previously assigned supply voltage corresponding to the performance interval).
摘要翻译： 公开了设计和制造集成电路的方法的实施例。 在预释放芯片设计过程中，该方法将集成电路设计的整个过程窗口细分为对应于可实现的性能的更小的连续间隔。 每个性能间隔通过为每个间隔分配不同的相应电源电压来独立优化性能与功耗。 然后在每个分配电压下的每个间隔关闭设计的时序。 在芯片制造之后，该方法测量根据设计制造的集成电路的性能。 使用这些性能测量，电路被分类到对应于每个性能间隔的适当标记的箱（例如，具有与性能间隔对应的性能目标和先前分配的电源电压）。
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8.发明申请公开(公告)号：US20080034337A1
公开(公告)日：2008-02-07
申请号：US11462508
申请日：2006-08-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed are embodiments of a method of designing and producing an integrated circuit. During the pre-release chip design process, the method subdivides the overall process window for an integrated circuit design into smaller successive intervals corresponding to achievable performance. Each performance interval is independently optimized for performance versus power by assigning to each interval a different corresponding supply voltage. Timing for the design is then closed for each interval at each assigned voltage. After chip manufacturing, the method measures the performance of the integrated circuits that are manufactured according to the design. Using these performance measurements, the circuits are sorted into bins corresponding to each performance interval and appropriately labeled (e.g., with the performance goal and previously assigned supply voltage corresponding to the performance interval).
摘要翻译： 公开了设计和制造集成电路的方法的实施例。 在预释放芯片设计过程中，该方法将集成电路设计的整个过程窗口细分为对应于可实现的性能的更小的连续间隔。 每个性能间隔通过为每个间隔分配不同的相应电源电压来独立优化性能与功耗。 然后在每个分配电压下的每个间隔关闭设计的时序。 在芯片制造之后，该方法测量根据设计制造的集成电路的性能。 使用这些性能测量，电路被分类到对应于每个性能间隔的适当标记的箱（例如，具有与性能间隔对应的性能目标和先前分配的电源电压）。
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9.发明授权Timing closure on multiple selective corners in a single statistical timing run 有权在单个统计计时运行中，在多个选择性角落定时关闭公开(公告)号：US08141012B2
公开(公告)日：2012-03-20
申请号：US12549061
申请日：2009-08-27
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Susan K. Lichtensteiger , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Susan K. Lichtensteiger , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks.
摘要翻译： 描述了在单个统计时序运行中覆盖多个选择性定时角的方法。 在一个实施例中，在涵盖无限制过程参数/环境条件的完整参数空间上运行单个统计时序分析。 统计时间分析的结果预计为所选角。 在具有最差松弛度的角落上进行定时关闭。
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公开(公告)号：US08086988B2
公开(公告)日：2011-12-27
申请号：US12467326
申请日：2009-05-18
申请人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
发明人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
CPC分类号： G06F17/5045 , G06F17/5031
摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.
摘要翻译： 公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。 该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。 基于JPD，生成相应的收益率曲线。 利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。 更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以生成利润模型。 基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力 。
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