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1.发明授权公开(公告)号：US07475366B2
公开(公告)日：2009-01-06
申请号：US11462508
申请日：2006-08-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed are embodiments of a method of designing and producing an integrated circuit. During the pre-release chip design process, the method subdivides the overall process window for an integrated circuit design into smaller successive intervals corresponding to achievable performance. Each performance interval is independently optimized for performance versus power by assigning to each interval a different corresponding supply voltage. Timing for the design is then closed for each interval at each assigned voltage. After chip manufacturing, the method measures the performance of the integrated circuits that are manufactured according to the design. Using these performance measurements, the circuits are sorted into bins corresponding to each performance interval and appropriately labeled (e.g., with the performance goal and previously assigned supply voltage corresponding to the performance interval).
摘要翻译： 公开了设计和制造集成电路的方法的实施例。 在预释放芯片设计过程中，该方法将集成电路设计的整个过程窗口细分为对应于可实现的性能的更小的连续间隔。 每个性能间隔通过为每个间隔分配不同的相应电源电压来独立优化性能与功耗。 然后在每个分配电压下的每个间隔关闭设计的时序。 在芯片制造之后，该方法测量根据设计制造的集成电路的性能。 使用这些性能测量，电路被分类到对应于每个性能间隔的适当标记的箱（例如，具有与性能间隔对应的性能目标和先前分配的电源电压）。
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2.发明申请公开(公告)号：US20080034337A1
公开(公告)日：2008-02-07
申请号：US11462508
申请日：2006-08-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed are embodiments of a method of designing and producing an integrated circuit. During the pre-release chip design process, the method subdivides the overall process window for an integrated circuit design into smaller successive intervals corresponding to achievable performance. Each performance interval is independently optimized for performance versus power by assigning to each interval a different corresponding supply voltage. Timing for the design is then closed for each interval at each assigned voltage. After chip manufacturing, the method measures the performance of the integrated circuits that are manufactured according to the design. Using these performance measurements, the circuits are sorted into bins corresponding to each performance interval and appropriately labeled (e.g., with the performance goal and previously assigned supply voltage corresponding to the performance interval).
摘要翻译： 公开了设计和制造集成电路的方法的实施例。 在预释放芯片设计过程中，该方法将集成电路设计的整个过程窗口细分为对应于可实现的性能的更小的连续间隔。 每个性能间隔通过为每个间隔分配不同的相应电源电压来独立优化性能与功耗。 然后在每个分配电压下的每个间隔关闭设计的时序。 在芯片制造之后，该方法测量根据设计制造的集成电路的性能。 使用这些性能测量，电路被分类到对应于每个性能间隔的适当标记的箱（例如，具有与性能间隔对应的性能目标和先前分配的电源电压）。
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公开(公告)号：US20130326459A1
公开(公告)日：2013-12-05
申请号：US13749851
申请日：2013-01-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31721 , G06F17/5031
摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.
摘要翻译： 一种优化集成电路（IC）芯片的功率和定时的方法，识别允许根据集成电路芯片设计产生的集成电路芯片在平均功耗目标和时序延迟目标内工作的多个有效的温度和电压组合。 这种方法从每个集成电路芯片的有效温度和电压组合中选择温度切割点，计算每个温度切断点的功率消耗量，并且基于功耗量调节温度切断点直到温度 切点实现了平均功耗目标。 接下来，该方法测试每个集成电路芯片，并将温度切割点记录在集成电路芯片的存储器中。
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公开(公告)号：US08839170B2
公开(公告)日：2014-09-16
申请号：US13749851
申请日：2013-01-25
IPC分类号： G06F17/50 , G01R31/317
CPC分类号： G06F17/5045 , G01R31/31721 , G06F17/5031
摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.
摘要翻译： 一种优化集成电路（IC）芯片的功率和定时的方法，识别允许根据集成电路芯片设计产生的集成电路芯片在平均功耗目标和时序延迟目标内工作的多个有效的温度和电压组合。 这种方法从每个集成电路芯片的有效温度和电压组合中选择温度切割点，计算每个温度切断点的功率消耗量，并且基于功耗量调节温度切断点直到温度 切点实现了平均功耗目标。 接下来，该方法测试每个集成电路芯片，并将温度切割点记录在集成电路芯片的存储器中。
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5.发明授权Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures 失效通过各种温度范围内的电压修改对集成电路进行功率和时序优化公开(公告)号：US08543960B1
公开(公告)日：2013-09-24
申请号：US13484451
申请日：2012-05-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/3004 , G01R31/3016 , G01R31/31725 , G06F17/5031
摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance.
摘要翻译： 一种通过修改提供给IC芯片的电压同时满足较低和较高温度范围内的功率消耗和定时延迟性能来优化集成电路（IC）芯片的功率和定时的方法，该集成电路（IC）芯片使用显示温度反转的IC技术 。 选择高电压，以满足整个温度范围内的闭合时序分析，以满足定时性能，并选择低电压以满足更高温度下的温度下降温度范围内的定时性能和功率性能 范围。 IC芯片在高电压下导通，并且当超过温度切断点时将高电压降低到低电压以满足功率性能同时保持定时性能。
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公开(公告)号：US10067184B2
公开(公告)日：2018-09-04
申请号：US13294243
申请日：2011-11-11
IPC分类号： G01R27/28 , G01R31/00 , G01R31/14 , G01R31/317
摘要： A method, test system and computer program product and system for voltage binning integrated circuit chips. The method includes selecting or changing a voltage bin of a set of voltages bins corresponding to frequency specification limits of an integrated circuit chip using functional testing of data paths of the integrated circuit chip.
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7.发明申请公开(公告)号：US20090295402A1
公开(公告)日：2009-12-03
申请号：US12131476
申请日：2008-06-02
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.
摘要翻译： 提供了一种表征具有至少一个电压岛和至少一个性能屏幕环形振荡器（PSRO）的芯片的性能的方法。 片上性能监视器（OCPM）被并入电压岛。 电压岛的性能测量仅在电源岛上产生。 性能屏幕环形振荡器（PSRO）的性能测量仅在电源电压岛下产生。 将性能屏幕环形振荡器（PSRO）的性能测量与片内性能监视器（OCPM）的性能测量进行比较，以确定由于电压岛引起的系统偏移。 使用由于电压岛引起的系统偏移来调整性能模型。
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8.发明申请公开(公告)号：US20090234777A1
公开(公告)日：2009-09-17
申请号：US12046237
申请日：2008-03-11
申请人： Thomas S. Barnett , Jeanne Paulette Spence Bickford , Nazmul Habib , Susan K. Lichtensteiger , Raymond J. Rosner
发明人： Thomas S. Barnett , Jeanne Paulette Spence Bickford , Nazmul Habib , Susan K. Lichtensteiger , Raymond J. Rosner
CPC分类号： G06F17/5036 , G06F17/5045 , G06F2217/14 , G06Q30/0283 , H01L22/20
摘要： An apparatus, method, and program product are provided to predict yield loss associated with performance screens or leakage screens. A leakage model is correlated to an on-chip measurement. Current limited yields are determined from the leakage model. A database is formed relating performance sigma cut-points to the circuit limited yields. A product is quoted based on the circuit limited yield for one of the performance sigma cut-points taken from the database. The quote is tied to the product design and testing.
摘要翻译： 提供了一种装置，方法和程序产品来预测与性能屏幕或泄漏屏幕相关联的屈服损失。 泄漏模型与片上测量相关。 目前有限的产量是根据泄漏模型确定的。 形成一个关于性能西格玛切割点与电路有限产量的数据库。 基于从数据库中获取的性能西格玛切割点之一的电路限制产量引用了产品。 报价与产品设计和测试有关。
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9.发明申请METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT 失效通过调节选择性电压激活切割点来优化功率的方法公开(公告)号：US20090228843A1
公开(公告)日：2009-09-10
申请号：US12041729
申请日：2008-03-04
申请人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuits and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests the operating speeds and power consumption levels of the integrated circuit devices. Then, the method adjusts the initial cut point to a final cut point based on the testing, to minimize the maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices.
摘要翻译： 在集成电路设计中优化功率使用的方法分析了预期由集成电路设计产生的多个操作速度切割点。 操作速度切割点用于将制造后的相同设计的集成电路器件分成相对较慢的集成电路和相对较快的集成电路器件。 该方法选择初始操作速度切割点以使相对较慢的集成电路和相对快速的集成电路器件的最大功率电平最小化。 然后，该方法使用集成电路设计制造集成电路器件，并测试集成电路器件的工作速度和功耗水平。 然后，该方法基于测试将初始切割点调整到最终切割点，以使相对较慢的集成电路和相对较快的集成电路器件的最大功率电平最小化。
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公开(公告)号：US09152168B2
公开(公告)日：2015-10-06
申请号：US13605050
申请日：2012-09-06
摘要： Methods and systems for system power estimation are provided. A method implemented in a computer infrastructure includes separating products into different segments. The method also includes calculating a power estimation for each segment based on operating conditions of each respective segment. The method further includes calculating an average system power estimation. At least one of the separating, calculating the power estimation, and calculating the average system power estimation is performed using a processor.
摘要翻译： 提供了系统功率估计的方法和系统。 在计算机基础设施中实现的方法包括将产品分成不同的段。 该方法还包括基于每个相应段的操作条件来计算每个段的功率估计。 该方法还包括计算平均系统功率估计。 使用处理器执行分离，计算功率估计和计算平均系统功率估计中的至少一个。
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