公开(公告)号：US5826109A

公开(公告)日：1998-10-20

申请号：US747197

申请日：1996-11-12

申请人： Jeffery M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Robert W. Martell

发明人： Jeffery M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth ,  Robert W. Martell

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/18

CPC分类号： G06F12/0859 ,  G06F9/3824 ,  G06F9/3834

摘要： The present invention provides for executing load instructions with a processor having a non-blocking cache memory, wherein individual load operations are dispatched to the cache memory and the cache memory signals the prevent the load operation from being sent to external memory when the load operation misses the cache memory and there is already a currently pending bus cycle to the same cache line. This helps reduce bus traffic on the external bus.

摘要翻译： 本发明提供用具有非阻塞高速缓冲存储器的处理器执行加载指令，其中单独的加载操作被分派到高速缓冲存储器，并且高速缓冲存储器发出信号，以防止当加载操作错过时将加载操作发送到外部存储器 高速缓存存储器并且已经存在当前待处理的总线周期到同一高速缓存行。 这有助于减少外部总线上的总线流量。

公开(公告)号：US5604878A

公开(公告)日：1997-02-18

申请号：US513679

申请日：1995-08-01

申请人： Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F13/00

CPC分类号： G06F9/3873 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.

摘要翻译： 执行可能参与回写冲突的功能单位的管道延长，以避免冲突。 提供逻辑电路用于比较两个并发执行的执行单元管线的深度，以确定冲突是否会发展。 当看来两个执行单元将尝试同时回写时，将指示具有较短流水线的执行单元向其流水线添加一个阶段，将其结果存储在一个时钟周期的延迟缓冲器中。 冲突解决后，延长给定功能单位管道的指示将被撤销。 多级执行单元被设计为用信号通知保留站来延迟各种指令的发送以避免执行单元之间的冲突。

公开(公告)号：US5546597A

公开(公告)日：1996-08-13

申请号：US203050

申请日：1994-02-28

申请人： Robert W. Martell ,  Glenn J. Hinton ,  Michael A. Fetterman ,  David B. Papworth ,  Robert P. Colwell ,  Andrew F. Glew

发明人： Robert W. Martell ,  Glenn J. Hinton ,  Michael A. Fetterman ,  David B. Papworth ,  Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/38 ,  G06F9/345

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： An instruction dispatch circuit is disclosed that improves instruction execution throughput for a processor. The instruction dispatch circuit comprises an instruction buffer with a plurality of instruction entries and a content addressable memory array having at least one cam entry corresponding to each instruction entry. Each cam entry stores at least one source tag for the corresponding instruction entry. The content addressable memory array matches to a result tag from an execution circuit over a result bus, wherein the execution circuit transfers the result tag over the result bus at least one clock cycle before transferring a corresponding result data value over the result bus. Each cam entry generates a cam match signal used to determine whether data dependent instruction are ready for dispatch.

摘要翻译： 公开了一种提高处理器的指令执行吞吐量的指令调度电路。 指令调度电路包括具有多个指令条目的指令缓冲器和具有对应于每个指令条目的至少一个凸轮条目的内容可寻址存储器阵列。 每个凸轮条目存储用于相应指令条目的至少一个源标签。 内容可寻址存储器阵列通过结果总线与来自执行电路的结果标签相匹配，其中执行电路在通过结果总线传送相应的结果数据值之前至少一个时钟周期在结果总线上传送结果标签。 每个凸轮条目产生一个凸轮匹配信号，用于确定数据相关指令是否准备好进行发送。

公开(公告)号：US06393550B1

公开(公告)日：2002-05-21

申请号：US08532225

申请日：1995-09-19

申请人： Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F930

CPC分类号： G06F9/30167 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： Maximum throughput or “back-to-back” scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.

摘要翻译： 通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。 这两个操作通过多种机制来实现。 用于确定源操作数的可用性以及因此用于调度到可用执行单元的依赖指令的准备状态的一种机制依赖于在源操作数为退休或即时值时在分配期间早期设置源有效位。 这允许保留站的就绪逻辑开始调度发送指令。

公开(公告)号：US5809325A

公开(公告)日：1998-09-15

申请号：US676528

申请日：1996-07-09

申请人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

发明人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/384 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891

摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.

公开(公告)号：US6101597A

公开(公告)日：2000-08-08

申请号：US176370

申请日：1993-12-30

申请人： Robert P. Colwell ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Robert P. Colwell ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3824 ,  G06F9/383

摘要： Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the prospective determination of the availability of a source operand before the operand itself is actually computed as a result of the execution of another instruction. Storage addresses of the source operands of an instruction are stored in a content addressable memory (CAM). Before an instruction is executed and its result data written back, the storage location address of the result is provided to the CAM and associatively compared with the source operand addresses stored therein. A CAM match and its accompanying match bit indicate that the result of the instruction to be executed will provide a source operand to the dependent instruction waiting in the reservation station. Using a bypass mechanism, if the operand is computed after dispatch of the dependent instruction, then the source operand is provided directly from the execution unit computing the source operand to a source operand input of the execution unit executing the dependent instruction.

摘要翻译： 通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。 这两个操作通过多个机制来实现。 用于确定源操作数的可用性以及因此用于发送到可用执行单元的依赖指令的准备的机制依赖于在操作数本身实际计算之前源操作数的可用性的预期确定 执行另一条指令。 指令的源操作数的存储地址存储在内容可寻址存储器（CAM）中。 在执行指令并且其结果数据被写回之前，将结果的存储位置地址提供给CAM并与存储在其中的源操作数地址相关联地进行比较。 CAM匹配及其伴随的匹配位指示要执行的指令的结果将为在保留站等待的从属指令提供源操作数。 使用旁路机制，如果在分派依赖指令之后计算操作数，则将操作数从执行单元直接提供到计算源操作数到执行依赖指令的执行单元的源操作数输入。

公开(公告)号：US5842036A

公开(公告)日：1998-11-24

申请号：US954444

申请日：1997-10-20

申请人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

发明人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/384 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891

摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.

公开(公告)号：US5555432A

公开(公告)日：1996-09-10

申请号：US293388

申请日：1994-08-19

申请人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

发明人： Glenn J. Hinton ,  Robert W. Martell ,  Michael A. Fetterman ,  David B. Papworth ,  James L. Schwartz

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/384 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891

摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.

摘要翻译： 公开了一种包括执行单元，存储单元和调度器的乱序执行处理器。 存储单元存储等待执行所需资源的可用性的指令。 调度器周期性地确定执行每个指令所需的资源是否可用，如果是，则将该指令分派到执行单元。 执行单元在实际可用的硬件资源之前指示诸如功能单元和写回端口的硬件资源的未来可用性数个时钟周期。 调度器基于硬件资源的未来可用性的指示来确定执行指令所需的资源的可用性，并且分派用于执行的指令。 无序执行处理器还包括在实际完成执行之前确定源指令执行的多个时钟周期的未来完成的装置。 调度器调度执行需要对操作数的这种源指令之一的执行结果的数据相关指令。 一旦源指令的执行结果可用，旁路多路复用器将执行结果旁路到分派的数据相关指令中。 旁路复用器将具有完全组合的操作数的数据相关指令发送到执行单元以供执行。

公开(公告)号：US5553256A

公开(公告)日：1996-09-03

申请号：US464571

申请日：1995-06-05

申请人： Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F9/06

CPC分类号： G06F9/30167 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.

摘要翻译： 通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。 这两个操作通过多种机制来实现。 用于确定源操作数的可用性以及因此用于调度到可用执行单元的依赖指令的准备状态的一种机制依赖于在源操作数为退休或即时值时在分配期间早期设置源有效位。 这允许保留站的就绪逻辑开始调度发送指令。

公开(公告)号：US5519864A

公开(公告)日：1996-05-21

申请号：US172737

申请日：1993-12-27

申请人： Robert W. Martell ,  Glenn J. Hinton

发明人： Robert W. Martell ,  Glenn J. Hinton

IPC分类号： G06F9/38 ,  G06F9/06

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/3857

摘要： Entries in a reservation station are efficiently scanned to find data-ready instructions for dispatch. A pseudo-FIFO scheduling approach is implemented wherein, rather than scanning every entry in the reservation station, the reservation station is segmented into groups of entries with each entry being scanned to determine which has the oldest entry in it. It is from the group of entries having the oldest entry that a ready pointer is cycled to search for data-ready instructions for dispatch to waiting execution units.

摘要翻译： 有效地扫描保留站中的条目以查找数据就绪指令进行发送。 实现伪FIFO调度方法，其中，不是扫描保留站中的每个条目，保留站被分段成条目组，其中每个条目被扫描以确定哪个条目具有其中最早的条目。 来自具有最早条目的条目组可以循环准备好的指针以搜索用于发送到等待执行单元的数据就绪指令。