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    Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system
    7.
    发明授权
    Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system 失效
    在无序执行计算机系统上缓存存储数据的方法和装置

    公开(公告)号：US5588126A

    公开(公告)日：1996-12-24

    申请号：US446030

    申请日：1995-05-19

    申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth

    发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  David B. Papworth

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3834

    摘要： In an out-of-order execution computer system, a store buffer is conditionally signaled to output buffered store data of buffered memory store operations, when a buffered memory load operation is being executed. The determination on whether to signal the store buffer or not is made using control information that includes the allocation state of the store buffer at the time the memory load operation being executed was issued. The allocation state includes the identification of the buffer slot storing the last memory store operation stored into the store buffer, and the wraparound state of a circular wraparound allocation approach employed to allocate buffer slots to the memory store operations, at the time the memory load operation being executed was issued.

    摘要翻译： 在无序执行计算机系统中，当执行缓冲存储器加载操作时，存储缓冲器有条件地发信号通知缓冲存储器存储操作的缓冲存储数据。 使用包含在执行存储器加载操作的时刻存储缓冲器的分配状态的控制信息来确定是否发出存储缓冲器的信号。 分配状态包括存储存储到存储缓冲器中的最后存储器存储操作的缓冲器槽的标识，以及在存储器加载操作时用于将缓冲器时隙分配给存储器存储操作的循环环绕分配方法的环绕状态 正在执行中。

    Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers
    10.
    发明授权
    Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers 失效
    具有数据和标签数组的高速缓冲存储器系统以及具有多个行缓冲器的多用途缓冲器组件

    公开(公告)号：US5680572A

    公开(公告)日：1997-10-21

    申请号：US680109

    申请日：1996-07-15

    申请人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

    发明人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0859

    摘要： A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.

    摘要翻译： 具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。 每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。 当缓存填充完成时，如果内存位置是可高速缓存的，并且缓存填充正在进行时，缓存线尚未被窥探，则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。 此外，填充缓冲区被组织并提供有足够的地址和数据端口以及选择器，以允许填充缓冲区响应后续处理器负载和存储，以及在高速缓存填充正在进行时触发其缓存行的外部监听。 因此，数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听，而无需停止处理器。