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公开(公告)号：US07733161B2
公开(公告)日：2010-06-08
申请号：US12031729
申请日：2008-02-15
CPC分类号： H02M3/07
摘要： A voltage boost system, IC and design structure are disclosed for boosting a supply voltage while preventing forward biasing of n-well structures. The voltage boost system may include a first voltage boost circuit producing a first boosted voltage using at least one voltage boost sub-circuit, each of the at least one voltage boost sub-circuit having an output passgate in an n-well; a second voltage boost circuit producing a second boosted voltage, the n-well of each output passgate being biased using the second boosted voltage, wherein the second boosted voltage is greater than the first boosted voltage. Voltage boost sub-circuits may use gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used.
摘要翻译： 公开了升压系统，IC和设计结构，用于提高电源电压，同时防止n阱结构的向前偏置。 升压系统可以包括使用至少一个升压子电路产生第一升压电压的第一升压电路，所述至少一个升压子电路中的每一个在n阱中具有输出通路; 产生第二升压电压的第二升压电路，使用第二升压电压对每个输出通道的n阱进行偏置，其中第二升压电压大于第一升压电压。 电压升压子电路可以使用栅极控制电路来减小栅极氧化物应力，从而允许使用较低电压电平的FET。
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2.发明授权Two stage voltage boost circuit with precharge circuit preventing leakage, IC and design structure 失效具有预充电电路的两级升压电路可防止漏电，集成电路和设计结构公开(公告)号：US07710195B2
公开(公告)日：2010-05-04
申请号：US12031731
申请日：2008-02-15
CPC分类号： H02M3/073
摘要： A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage and a second stage for boosting the first boosted voltage to a second boosted voltage. Each stage may include a passgate and a gate control circuit for generating an on-state gate voltage level for the respective passgate adjusted to reduce gate oxide voltage stress on the passgate. The circuit may also include a precharge circuit for coupling a voltage on a high node of the second stage to a gate node of a precharge transistor thereof for disabling the precharge transistor and preventing leakage back to a power supply voltage.
摘要翻译： 公开了两级升压电路IC和设计结构，用于使用栅极控制电路来提高电源电压以减小栅极氧化物应力，从而允许使用较低电压电平的FET。 升压电路可以包括用于将电源电压升压到第一升压电压的第一级和用于将第一升压电压升压到第二升压电压的第二级。 每个级可以包括一个通道和一个栅极控制电路，用于产生用于相应通路的导通状态栅极电压电平，被调节以减小通路上的栅极氧化物电压应力。 电路还可以包括用于将第二级的高节点上的电压耦合到其预充电晶体管的栅极节点的预充电电路，用于禁止预充电晶体管并防止漏电回到电源电压。
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公开(公告)号：US20090206915A1
公开(公告)日：2009-08-20
申请号：US12031725
申请日：2008-02-15
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage; a first passgate coupled to the first stage; a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate; a second stage for boosting the first boosted voltage to a second boosted voltage; a second passgate coupled to the second stage, and a gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second pass-gate.
摘要翻译： 公开了两级升压电路IC和设计结构，用于使用栅极控制电路来提高电源电压以减小栅极氧化物应力，从而允许使用较低电压电平的FET。 升压电路可以包括用于将电源电压升压到第一升压电压的第一级; 耦合到第一级的第一传递门; 第一栅极控制电路，用于产生用于第一通道的导通状态栅极电压电平，该栅极电压电平被调整以减小通路上的栅极氧化物电压应力; 第二级，用于将第一升压电压升压到第二升压电压; 耦合到第二级的第二传递门和用于产生用于第二通道的导通状态栅极电压电平的栅极控制电路，该栅极电压电平被调整以减小第二栅极上的栅极氧化物电压应力。
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4.发明申请Two Stage Voltage Boost Circuit With Precharge Circuit Preventing Leakage, IC and Design Structure 失效具有预充电电路的两级电压升压电路，防止泄漏，IC和设计结构公开(公告)号：US20090206917A1
公开(公告)日：2009-08-20
申请号：US12031731
申请日：2008-02-15
IPC分类号： G05F1/10
CPC分类号： H02M3/073
摘要： A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage and a second stage for boosting the first boosted voltage to a second boosted voltage. Each stage may include a passgate and a gate control circuit for generating an on-state gate voltage level for the respective passgate adjusted to reduce gate oxide voltage stress on the passgate. The circuit may also include a precharge circuit for coupling a voltage on a high node of the second stage to a gate node of a precharge transistor thereof for disabling the precharge transistor and preventing leakage back to a power supply voltage.
摘要翻译： 公开了两级升压电路IC和设计结构，用于使用栅极控制电路来提高电源电压以减小栅极氧化物应力，从而允许使用较低电压电平的FET。 升压电路可以包括用于将电源电压升压到第一升压电压的第一级和用于将第一升压电压升压到第二升压电压的第二级。 每个级可以包括一个通道和一个栅极控制电路，用于产生用于相应通路的导通状态栅极电压电平，被调节以减小通路上的栅极氧化物电压应力。 电路还可以包括用于将第二级的高节点上的电压耦合到其预充电晶体管的栅极节点的预充电电路，用于禁止预充电晶体管并防止漏电回到电源电压。
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公开(公告)号：US07737766B2
公开(公告)日：2010-06-15
申请号：US12031725
申请日：2008-02-15
CPC分类号： H02M3/07
摘要： A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage; a first passgate coupled to the first stage; a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate; a second stage for boosting the first boosted voltage to a second boosted voltage; a second passgate coupled to the second stage, and a second gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second passgate.
摘要翻译： 公开了两级升压电路IC和设计结构，用于使用栅极控制电路来提高电源电压以减小栅极氧化物应力，从而允许使用较低电压电平的FET。 升压电路可以包括用于将电源电压升压到第一升压电压的第一级; 耦合到第一级的第一传递门; 第一栅极控制电路，用于产生用于第一通道的导通状态栅极电压电平，该栅极电压电平被调整以减小通路上的栅极氧化物电压应力; 第二级，用于将第一升压电压升压到第二升压电压; 耦合到第二级的第二传递门和用于产生用于第二通道的导通状态栅极电压电平的第二栅极控制电路，其被调节以减小第二通道上的栅极氧化物电压应力。
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公开(公告)号：US20090206916A1
公开(公告)日：2009-08-20
申请号：US12031729
申请日：2008-02-15
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A voltage boost system, IC and design structure are disclosed for boosting a supply voltage while preventing forward biasing of n-well structures. The voltage boost system may include a first voltage boost circuit producing a first boosted voltage using at least one voltage boost sub-circuit, each of the at least one voltage boost sub-circuit having an output passgate in an n-well; a second voltage boost circuit producing a second boosted voltage, the n-well of each output passgate being biased using the second boosted voltage, wherein the second boosted voltage is greater than the first boosted voltage. Voltage boost sub-circuits may use gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used.
摘要翻译： 公开了升压系统，IC和设计结构，用于提高电源电压，同时防止n阱结构的向前偏置。 升压系统可以包括使用至少一个升压子电路产生第一升压电压的第一升压电路，所述至少一个升压子电路中的每一个在n阱中具有输出通路; 产生第二升压电压的第二升压电路，使用第二升压电压对每个输出通道的n阱进行偏置，其中第二升压电压大于第一升压电压。 电压升压子电路可以使用栅极控制电路来减小栅极氧化物应力，从而允许使用较低电压电平的FET。
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公开(公告)号：US07401281B2
公开(公告)日：2008-07-15
申请号：US10707971
申请日：2004-01-29
CPC分类号： G11C29/14 , G01R31/31724 , G01R31/3187 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401
摘要： Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.
摘要翻译： 公开了一种用于嵌入式存储器阵列的混合内置自测（BIST）架构，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并使用BIST指令集与多个嵌入式存储器阵列进行通信。 一个高速测试逻辑块被并入被测试的每个嵌入式存储器阵列中，并以更高的频率在本地处理从独立BIST逻辑控制器接收的BIST指令。 高速测试逻辑包括用于将BIST指令的频率从较低频率增加到较高频率的乘法器。 独立的BIST逻辑控制器使多个嵌入式存储器阵列中的多个更高速的测试逻辑结构能够实现。
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公开(公告)号：US06233184B1
公开(公告)日：2001-05-15
申请号：US09191954
申请日：1998-11-13
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。
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公开(公告)号：US07237165B2
公开(公告)日：2007-06-26
申请号：US10994496
申请日：2004-11-22
申请人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
发明人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/26 , G11C2207/104
摘要： A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.
摘要翻译： 用于测试DRAM的系统包括DRAM块，该系统还包括用于为每个DRAM块生成测试数据模式的基于处理器的内置自测试系统，将测试数据模式写入DRAM块，执行 暂停预定时间段，并且从DRAM块执行所得数据模式的读取。 对于每个DRAM块，在执行暂停预定时间段之前执行将测试图案写入DRAM块的执行，并且在执行结果之后执行从DRAM块读取得到的数据模式 在预定时间段中的暂停，以及两个或更多个DRAM块的预定时间段的暂停的至少一部分在时间上重叠。
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公开(公告)号：US5463335A
公开(公告)日：1995-10-31
申请号：US969594
申请日：1992-10-30
CPC分类号： H03K17/223
摘要： A power up detection circuit is provided which includes a power supply terminal, an output terminal, an impedance device coupling the output terminal to the power supply terminal and a latch including a first inverter having a first device connected between the output terminal and a point of reference potential and a second device connected between the output terminal and the power supply terminal, the devices are designed so that subthreshold current passing through the first device is greater than the effective subthreshold current passing through the impedance device and the second device, and a second inverter including third and fourth devices which are designed so that a smaller subthreshold current passes through the third device than the subthreshold current passing through the fourth device. The power up circuit may further include a capacitor connected between the power supply terminal and gate electrodes of the first and second devices.
摘要翻译： 提供了一种上电检测电路，其包括电源端子，输出端子，将输出端子耦合到电源端子的阻抗装置和包括第一反相器的锁存器，第一反相器具有连接在输出端子与点 参考电位和连接在输出端子和电源端子之间的第二器件，器件被设计成使得通过第一器件的亚阈值电流大于通过阻抗器件和第二器件的有效亚阈值电流，并且第二器件 逆变器包括第三和第四器件，其被设计为使得比通过第四器件的亚阈值电流更小的亚阈值电流通过第三器件。 上电电路还可以包括连接在第一和第二器件的电源端子和栅电极之间的电容器。
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