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    Metal-insulator-metal capacitor for copper damascene process and method of forming the same
    3.
    发明授权
    Metal-insulator-metal capacitor for copper damascene process and method of forming the same 失效
    用于铜镶嵌工艺的金属 - 绝缘体 - 金属电容器及其形成方法

    公开(公告)号：US06259128B1

    公开(公告)日：2001-07-10

    申请号：US09298122

    申请日：1999-04-23

    申请人： Eric Adler ,  Henry W. Trombley

    发明人： Eric Adler ,  Henry W. Trombley

    IPC分类号： H01L2972

    CPC分类号： H01L28/60

    摘要： A capacitor structure formed on a semiconductor substrate may include a first interconnect wiring (such as copper damascene) and a first conductive barrier layer in contact with the first interconnect wiring. A first capacitor plate, a capacitor dielectric structure and a second capacitor plate may also be included over the first conductive barrier layer. A second conductive barrier layer may be formed on the second capacitor plate and a second planar insulating structure may be formed over the second capacitor plate. Finally, a second interconnect wiring may be embedded within a second planar insulator structure.

    摘要翻译： 形成在半导体衬底上的电容器结构可以包括与第一互连布线接触的第一互连布线（例如铜镶嵌）和第一导电阻挡层。 第一电容器板，电容器介质结构和第二电容器板也可以包括在第一导电阻挡层上。 可以在第二电容器板上形成第二导电阻挡层，并且可以在第二电容器板上形成第二平面绝缘结构。 最后，第二互连布线可嵌入第二平面绝缘体结构内。

    METHODS TO SELECT GOLDEN DEVICES FOR DEVICE MODEL EXTRACTIONS
    4.
    发明申请
    METHODS TO SELECT GOLDEN DEVICES FOR DEVICE MODEL EXTRACTIONS 有权
    选择用于设备模型提取的金属器件的方法

    公开(公告)号：US20090210176A1

    公开(公告)日：2009-08-20

    申请号：US12031374

    申请日：2008-02-14

    申请人： Henry W. Trombley ,  Zhenrong Jin

    发明人： Henry W. Trombley ,  Zhenrong Jin

    IPC分类号： G06F17/18 ,  G01R15/00

    CPC分类号： G01R31/2894 ,  G01R35/007

    摘要： Methods for selecting one or more golden devices on a golden wafer that exhibit a smooth length and width scaling behavior. Test devices of differing geometry and carried on different chips of the golden wafer are screened with single point measurements of electrical performance. Based upon a statistical analysis of these single point measurements, chips are selected that carry the respective golden device of each given geometry that exhibits optimum electrical performance referenced to a selection criterion. Golden devices identified by the selection process are extensively characterized with a more comprehensive electrical measurement. The parameters derived from these more extensive test measurements on the golden devices are then used for refining a device model for a circuit simulation.

    摘要翻译： 在金色晶片上选择一个或多个呈现平滑长度和宽度缩放行为的黄金装置的方法。 具有不同几何尺寸并承载在金色晶片的不同芯片上的测试装置用电性能的单点测量进行屏蔽。 基于对这些单点测量的统计分析，选择携带基于选择标准表现出最佳电性能的每个给定几何体的相应黄金装置的芯片。 通过选择过程识别的黄金设备的广泛特点是具有更全面的电气测量。 然后，使用从金装置上的这些更广泛的测试测量得到的参数用于精炼用于电路仿真的器件模型。

    Modeling small mosfets using ensemble devices
    5.
    发明授权
    Modeling small mosfets using ensemble devices 失效
    使用集成设备建模小型mosfet

    公开(公告)号：US07353473B2

    公开(公告)日：2008-04-01

    申请号：US11381613

    申请日：2006-05-04

    申请人： Robinson E. Pino ,  Henry W. Trombley ,  Josef S. Watts

    发明人： Robinson E. Pino ,  Henry W. Trombley ,  Josef S. Watts

    IPC分类号： G06F17/50 ,  G06F17/10

    CPC分类号： G06F17/5036

    摘要： A method of modeling statistical variation of field effect transistors having fingers physically measures characteristics of existing transistors and extracts a scaled simulation based on the characteristics of the existing transistors using a first model. The method creates synthetic single finger data using the scaled simulation. The method physically measures characteristics of existing pairs of matched transistors and extracts random dopant fluctuations from the characteristics of the existing pairs of matched transistors using a second model that is different than the first model. The method extracts a single finger from the synthetic single finger data and the random dopant fluctuations using the first model. The method can also create an ensemble model by determining the skew between a typical single device model and a typical ensemble model. The method adjusts parameters of the first model to cause the single finger to match targets for the single finger. Also, the method produces the centered scalable single finger model (model C) after the adjustments are complete.

    摘要翻译： 具有手指的场效应晶体管的统计变化的模型的方法物理地测量现有晶体管的特性，并且基于使用第一模型的现有晶体管的特性提取缩放模拟。 该方法使用缩放模拟创建合成单指数据。 该方法物理地测量现有的匹配晶体管对的特性，并使用不同于第一模型的第二模型从现有的匹配晶体管对的特性中提取随机掺杂物波动。 该方法使用第一模型从合成单指数据和随机掺杂剂波动提取单个手指。 该方法还可以通过确定典型的单个设备模型和典型的集合模型之间的偏差来创建集合模型。 该方法调整第一个模型的参数，使单个手指匹配单个手指的目标。 此外，在调整完成后，该方法产生居中的可伸缩单指模型（模型C）。

    Extracting consistent compact model parameters for related devices
    6.
    发明授权
    Extracting consistent compact model parameters for related devices 有权
    为相关设备提取一致的紧凑型模型参数

    公开(公告)号：US08010930B2

    公开(公告)日：2011-08-30

    申请号：US12344724

    申请日：2008-12-29

    申请人： Henry W. Trombley ,  Josef S. Watts

    发明人： Henry W. Trombley ,  Josef S. Watts

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method, apparatus and program product are provided for extracting parameters for compact models for semiconductor devices. A first set of parameters associated with first and second semiconductor devices is defined and has the same value for all devices. A second set of parameters associated with the semiconductor devices is defined having values that differ among the devices. Data is measured from the semiconductor devices related to the first and second set of parameters. A mathematical relationship is established between the measured data, and the values of the second set of parameters are adjusted to fit the established mathematical relationship. The mathematical relationship may also be a correlation of the measured data from the first semiconductor device with the measured data from the second semiconductor device creating a data set for parameter extraction. Parameters may then be extracted from the data set related to the first and second semiconductor devices.

    摘要翻译： 提供了用于提取用于半导体器件的紧凑模型的参数的方法，装置和程序产品。 定义与第一和第二半导体器件相关联的第一组参数，并且对于所有器件具有相同的值。 与半导体器件相关联的第二组参数被定义为具有在器件之间不同的值。 从与第一和第二组参数相关的半导体器件测量数据。 在测量数据之间建立数学关系，并调整第二组参数的值以适应已建立的数学关系。 数学关系还可以是来自第一半导体器件的测量数据与来自第二半导体器件的测量数据的相关性，从而创建用于参数提取的数据集。 然后可以从与第一和第二半导体器件相关的数据集中提取参数。

    Solutions for modeling spatially correlated variations in an integrated circuit
    7.
    发明授权
    Solutions for modeling spatially correlated variations in an integrated circuit 有权
    用于建模集成电路中空间相关变化的解决方案

    公开(公告)号：US08903697B2

    公开(公告)日：2014-12-02

    申请号：US13233176

    申请日：2011-09-15

    申请人： Henry W. Trombley ,  Josef S. Watts

    发明人： Henry W. Trombley ,  Josef S. Watts

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/10

    摘要： A computer-implemented method for modeling Spatially Correlated Variation (SCV) in a design of an Integrated Circuit (IC) is disclosed. In one embodiment, the method includes: generating a set of coefficient values for a position dependent SCV function, the set of coefficient values being selected from a set of random variables; obtaining a set of coordinates defining a position of each of a plurality of devices in a defined field; evaluating the position dependent SCV function to determine a device attribute variation for each of the plurality of devices based upon the coordinates of each of the plurality of devices; modifying at least one model parameter based upon the evaluation of the position dependent SCV function; and running a circuit simulation using the at least one modified model parameter.

    摘要翻译： 公开了一种用于在集成电路（IC）的设计中对空间相关变化（SCV）建模的计算机实现的方法。 在一个实施例中，该方法包括：产生用于位置相关SCV函数的一组系数值，该系数值集合是从一组随机变量中选择的; 在定义的字段中获得定义多个设备中的每一个的位置的坐标集合; 基于所述多个设备中的每一个的坐标来评估所述位置相关SCV功能以确定所述多个设备中的每一个的设备属性变化; 基于位置相关SCV功能的评估来修改至少一个模型参数; 以及使用所述至少一个修改的模型参数来运行电路仿真。

    SOLUTIONS FOR MODELING SPATIALLY CORRELATED VARIATIONS IN AN INTEGRATED CIRCUIT
    8.
    发明申请
    SOLUTIONS FOR MODELING SPATIALLY CORRELATED VARIATIONS IN AN INTEGRATED CIRCUIT 有权
    用于在集成电路中建模空间相关变化的解决方案

    公开(公告)号：US20130073266A1

    公开(公告)日：2013-03-21

    申请号：US13233176

    申请日：2011-09-15

    申请人： Henry W. Trombley ,  Josef S. Watts

    发明人： Henry W. Trombley ,  Josef S. Watts

    IPC分类号： G06F17/50 ,  G06F17/10

    CPC分类号： G06F17/5068 ,  G06F2217/10

    摘要： A computer-implemented method for modeling Spatially Correlated Variation (SCV) in a design of an Integrated Circuit (IC) is disclosed. In one embodiment, the method includes: generating a set of coefficient values for a position dependent SCV function, the set of coefficient values being selected from a set of random variables; obtaining a set of coordinates defining a position of each of a plurality of devices in a defined field; evaluating the position dependent SCV function to determine a device attribute variation for each of the plurality of devices based upon the coordinates of each of the plurality of devices; modifying at least one model parameter based upon the evaluation of the position dependent SCV function; and running a circuit simulation using the at least one modified model parameter.

    摘要翻译： 公开了一种用于在集成电路（IC）的设计中对空间相关变化（SCV）建模的计算机实现的方法。 在一个实施例中，该方法包括：产生用于位置相关SCV函数的一组系数值，该系数值集合是从一组随机变量中选择的; 在定义的字段中获得定义多个设备中的每一个的位置的坐标集合; 基于所述多个设备中的每一个的坐标来评估所述位置相关SCV功能以确定所述多个设备中的每一个的设备属性变化; 基于位置相关SCV功能的评估来修改至少一个模型参数; 以及使用所述至少一个修改的模型参数来运行电路仿真。

    Anti-reflective coatings for spatial light modulators
    9.
    发明授权
    Anti-reflective coatings for spatial light modulators 有权
    用于空间光调制器的防反射涂层

    公开(公告)号：US06282010B1

    公开(公告)日：2001-08-28

    申请号：US09306271

    申请日：1999-05-06

    申请人： Frank C. Sulzbach ,  Brian L. Ray ,  G. Sreenivas ,  Duane E. Carter ,  Henry W. Trombley ,  Austin L. Huang ,  James D. Huffman

    发明人： Frank C. Sulzbach ,  Brian L. Ray ,  G. Sreenivas ,  Duane E. Carter ,  Henry W. Trombley ,  Austin L. Huang ,  James D. Huffman

    IPC分类号： G02F103

    CPC分类号： G02F1/133502

    摘要： A spatial light modulator with an anti-reflective coating (ARC) 100 integrated into its structure. The manufacturing of the device is altered to include deposition of an ARC 100, and any necessary patterning and etching to allow the elements of the array to operate properly. The ARC could reside in several places of the element structure including over the addressing circuitry 26, over a middle layer 32 or on the underside of the reflective structure 10. Micromechanical spatial light modulators, as well as non-moving modulators, such as reflective and transmissive LCD modulators can use the invention.

    摘要翻译： 具有集成到其结构中的抗反射涂层（ARC）100的空间光调制器。 改变器件的制造以包括ARC 100的沉积，以及任何必要的图案化和蚀刻，以允许阵列的元件正常工作。 ARC可以驻留在元件结构的多个位置，包括在寻址电路26上方，中间层32上或反射结构10的下侧。微机械空间光调制器以及非移动调制器，例如反射和 透射式LCD调制器可以使用本发明。

    Methods to select golden devices for device model extractions
    10.
    发明授权
    Methods to select golden devices for device model extractions 有权
    为设备型号提取选择黄金设备的方法

    公开(公告)号：US07818074B2

    公开(公告)日：2010-10-19

    申请号：US12031374

    申请日：2008-02-14

    申请人： Henry W. Trombley ,  Zhenrong Jin

    发明人： Henry W. Trombley ,  Zhenrong Jin

    IPC分类号： G05B13/02

    CPC分类号： G01R31/2894 ,  G01R35/007

    摘要： Methods for selecting one or more golden devices on a golden wafer that exhibit a smooth length and width scaling behavior. Test devices of differing geometry and carried on different chips of the golden wafer are screened with single point measurements of electrical performance. Based upon a statistical analysis of these single point measurements, chips are selected that carry the respective golden device of each given geometry that exhibits optimum electrical performance referenced to a selection criterion. Golden devices identified by the selection process are extensively characterized with a more comprehensive electrical measurement. The parameters derived from these more extensive test measurements on the golden devices are then used for refining a device model for a circuit simulation.

    摘要翻译： 在金色晶片上选择一个或多个呈现平滑长度和宽度缩放行为的黄金装置的方法。 具有不同几何尺寸并承载在金色晶片的不同芯片上的测试装置用电性能的单点测量进行屏蔽。 基于对这些单点测量的统计分析，选择携带基于选择标准表现出最佳电性能的每个给定几何体的相应黄金装置的芯片。 通过选择过程识别的黄金设备的广泛特点是具有更全面的电气测量。 然后，使用从金装置上的这些更广泛的测试测量得到的参数用于精炼用于电路仿真的器件模型。