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    Method of forming electrode of semiconductor device
    1.
    发明授权
    Method of forming electrode of semiconductor device 失效
    形成半导体器件电极的方法

    公开(公告)号：US5744398A

    公开(公告)日：1998-04-28

    申请号：US788107

    申请日：1997-01-23

    申请人： Jeong Soo Byun ,  Byung Hak Lee

    发明人： Jeong Soo Byun ,  Byung Hak Lee

    IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/78 ,  H01L21/44 ,  H01L21/48

    CPC分类号： H01L21/28518 ,  H01L21/28061

    摘要： A method of forming an electrode of a semiconductor device includes the steps of forming an insulating layer on a semiconductor substrate, forming a tungsten silicide layer on the insulating layer, implanting impurity ions into the tungsten silicide layer to form an impurity region in a lower portion of the tungsten silicide layer, and carrying out a heat treatment to the substrate on which the tungsten silicide layer is formed.

    摘要翻译： 形成半导体器件的电极的方法包括以下步骤：在半导体衬底上形成绝缘层，在绝缘层上形成硅化钨层，将杂质离子注入到硅化钨层中，以在下部形成杂质区 的硅化钨层，对其上形成有硅化钨层的基板进行热处理。

    Method for fabricating semiconductor device
    2.
    发明授权
    Method for fabricating semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US6096630A

    公开(公告)日：2000-08-01

    申请号：US949397

    申请日：1997-10-14

    申请人： Jeong Soo Byun ,  Byung Hak Lee

    发明人： Jeong Soo Byun ,  Byung Hak Lee

    IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/28061 ,  H01L21/823835

    摘要： Method for fabricating a semiconductor device, is disclosed, which is suitable for improving a resistivity, including the steps of forming a silicon layer on a substrate, forming a crystalline metal silicide layer on the silicon layer, forming an amorphous metal silicide layer by injecting ions into the crystalline metal silicide layer, and crystallizing the amorphous metal silicide by heat treating the amorphous metal silicide.

    摘要翻译： 公开了用于制造半导体器件的方法，其适于提高电阻率，包括在衬底上形成硅层的步骤，在硅层上形成结晶金属硅化物层，通过注入离子形成非晶金属硅化物层 进入结晶金属硅化物层，并通过热处理非晶金属硅化物使非晶金属硅化物结晶。

    Method for fabricating semiconductor device having improved step coverage and low resistivity contacts
    3.
    发明授权
    Method for fabricating semiconductor device having improved step coverage and low resistivity contacts 失效
    具有改善的台阶覆盖和低电阻率接触的半导体器件的制造方法

    公开(公告)号：US06221762B1

    公开(公告)日：2001-04-24

    申请号：US08949399

    申请日：1997-10-14

    申请人： Jeong Soo Byun ,  Byung Hak Lee

    发明人： Jeong Soo Byun ,  Byung Hak Lee

    IPC分类号： H01L214763

    CPC分类号： H01L21/28518

    摘要： A method for fabricating a semiconductor device improves step coverage and resistivity. The method includes the steps of forming a doped silicon layer on a substrate, forming a silicide layer containing more metal atoms than silicon atoms on the doped silicon layer, and heat treating in nitrogen to form a second silicide layer having a tetragonal phase crystal structure and a silicon nitride film on the top surface of the second silicide layer.

    摘要翻译： 半导体器件的制造方法提高了步骤覆盖率和电阻率。 该方法包括以下步骤：在衬底上形成掺杂硅层，在掺杂硅层上形成含有比硅原子更多的金属原子的硅化物层，并在氮气中热处理以形成具有四方晶相结构的第二硅化物层， 在第二硅化物层的顶表面上的氮化硅膜。

    Method for fabricating conductive line pattern for semiconductor device
    4.
    发明授权
    Method for fabricating conductive line pattern for semiconductor device 有权
    制造半导体器件导电线图案的方法

    公开(公告)号：US06599821B2

    公开(公告)日：2003-07-29

    申请号：US09793567

    申请日：2001-02-27

    申请人： Byung Hak Lee

    发明人： Byung Hak Lee

    IPC分类号： H01L213205

    CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L29/4941

    摘要： A method for fabricating a conductive line pattern for a semiconductor device including the steps of: forming a gate insulation film on the upper surface of a semiconductor substrate; forming a polysilicon layer on the upper surface of the gate insulation film; forming a WNx film on the upper surface of the polysilicon layer; forming a first insulation film on the upper surface of the WNx film; patterning the first insulation film, the WNx film and the polysilicon layer, to form a conductive line pattern; and selectively oxidizing the polysilicon layer. With the method, in view of forming the conductive line pattern in the WNx/poly-Si structure, the thermal treatment processes are reduced in number, so that the thermal stress applied to the conductive line pattern is diminished, and thus, a reliability of the semiconductor device is improved. In addition, as the thermal treatment processes are reduced in number, the processes are simplified, and accordingly a time required for fabricating the conductive line pattern of the semiconductor is decreased.

    摘要翻译： 一种用于半导体器件的导线图案的制造方法，包括以下步骤：在半导体衬底的上表面上形成栅极绝缘膜; 在栅极绝缘膜的上表面上形成多晶硅层; 在多晶硅层的上表面上形成WNx膜; 在WNx膜的上表面上形成第一绝缘膜; 图案化第一绝缘膜，WNx膜和多晶硅层，以形成导线图案; 并选择性地氧化多晶硅层。 利用该方法，从WNx / poly-Si结构中形成导线图案的观点出发，热处理工序数量减少，导致导线图案的热应力下降，可靠性 改善了半导体器件。 此外，随着热处理工艺的数量减少，工艺简化，因此制造半导体的导线图案所需的时间减少。

    Method for forming a gate electrode on a semiconductor substrate
    5.
    发明授权
    Method for forming a gate electrode on a semiconductor substrate 有权
    在半导体基板上形成栅电极的方法

    公开(公告)号：US06306743B1

    公开(公告)日：2001-10-23

    申请号：US09798942

    申请日：2001-03-06

    申请人： Byung Hak Lee

    发明人： Byung Hak Lee

    IPC分类号： H01L213205

    CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/28247

    摘要： A method for forming a gate electrode on a semiconductor substrate that includes forming a gate insulating layer on a semiconductor substrate, forming a polysilicon layer on the semiconductor substrate, forming a tungsten silicide layer on the polysilicon layer, forming a diffusion barrier layer on the tungsten silicide layer, forming a tungsten layer on the diffusion barrier layer, crystallizing the diffusion barrier layer, forming a first insulating layer on the tungsten layer, forming a gate electrode, forming an oxide layer, and forming a second insulating layer.

    摘要翻译： 一种在半导体衬底上形成栅电极的方法，包括在半导体衬底上形成栅极绝缘层，在半导体衬底上形成多晶硅层，在多晶硅层上形成硅化钨层，在钨层上形成扩散阻挡层 硅化物层，在扩散阻挡层上形成钨层，使扩散阻挡层结晶，在钨层上形成第一绝缘层，形成栅电极，形成氧化物层，形成第二绝缘层。

    Gate electrode in a semiconductor device and method for forming thereof
    7.
    发明授权
    Gate electrode in a semiconductor device and method for forming thereof 失效
    半导体器件中的栅电极及其形成方法

    公开(公告)号：US06432801B1

    公开(公告)日：2002-08-13

    申请号：US09556817

    申请日：2000-04-21

    申请人： Byung Hak Lee

    发明人： Byung Hak Lee

    IPC分类号： H01L213205

    CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/28247

    摘要： The present invention relates to a method for forming a gate electrode in a semiconductor device, which can improve GOI characteristics and allows for an effective suppression of metal silicide spike formation. This method includes the steps of forming a gate insulating film over a semiconductor substrate, forming a first semiconductor layer over the gate insulating film, forming a barrier layer over the first semiconductor layer to prevent formation of metal silicide spikes in the first semiconductor layer, forming a second semiconductor layer over the barrier layer, and forming a metal silicide layer over the second semiconductor layer.

    摘要翻译： 本发明涉及一种在半导体器件中形成栅电极的方法，其可以改善GOI特性并允许有效抑制金属硅化物尖峰形成。 该方法包括以下步骤：在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成第一半导体层，在第一半导体层上形成阻挡层，以防止在第一半导体层中形成金属硅化物尖峰，形成 在所述阻挡层上方的第二半导体层，以及在所述第二半导体层上形成金属硅化物层。

    Method for forming conductive line of semiconductor device
    8.
    发明授权
    Method for forming conductive line of semiconductor device 有权
    形成半导体器件导线的方法

    公开(公告)号：US06335297B1

    公开(公告)日：2002-01-01

    申请号：US09592438

    申请日：2000-06-12

    申请人： Chang Hee Han ,  Byung Hak Lee

    发明人： Chang Hee Han ,  Byung Hak Lee

    IPC分类号： H01L2131

    CPC分类号： H01L21/28061 ,  H01L21/2807 ,  H01L29/4925

    摘要： Method for forming a conductive line of a semiconductor device which has a high thermal stability and low electrical resistance includes the steps of forming an insulating layer on a semiconductor substrate, sequentially forming a semiconductor layer and a tungsten film on the insulating layer, nitrifying the tungsten film with heat treatment, and selectively etching the tungsten film and the semiconductor layer.

    摘要翻译： 用于形成具有高热稳定性和低电阻的半导体器件的导线的方法包括以下步骤：在半导体衬底上形成绝缘层，在绝缘层上依次形成半导体层和钨膜，硝化钨 膜，并且选择性地蚀刻钨膜和半导体层。

    Method for forming gate electrode of semiconductor device
    10.
    发明授权
    Method for forming gate electrode of semiconductor device 有权
    形成半导体器件栅电极的方法

    公开(公告)号：US06531394B1

    公开(公告)日：2003-03-11

    申请号：US09722820

    申请日：2000-11-28

    申请人： Byung Hak Lee

    发明人： Byung Hak Lee

    IPC分类号： H01L2144

    CPC分类号： H01L21/28061 ,  H01L21/265 ,  H01L21/321 ,  H01L29/4941

    摘要： A method for forming a gate electrode of a semiconductor device, which improves thermal stability of a tungsten/polysilicon structure. The method for forming a gate electrode of a semiconductor device includes: sequentially forming a first insulating film, a polysilicon layer and a tungsten layer on a semiconductor substrate; adding oxygen to the tungsten layer; forming a second insulating film on the tungsten layer to which oxygen is added; and selectively removing the second insulating film, the tungsten layer, the polysilicon layer and the first insulating film to form a gate electrode.

    摘要翻译： 一种形成半导体器件的栅电极的方法，其改善了钨/多晶硅结构的热稳定性。 形成半导体器件的栅电极的方法包括：在半导体衬底上依次形成第一绝缘膜，多晶硅层和钨层; 向钨层中加入氧气; 在添加有氧的钨层上形成第二绝缘膜; 并且选择性地去除第二绝缘膜，钨层，多晶硅层和第一绝缘膜以形成栅电极。