公开(公告)号：US06235628B1

公开(公告)日：2001-05-22

申请号：US09225545

申请日：1999-01-05

申请人： Fei Wang ,  Jerry Cheng

发明人： Fei Wang ,  Jerry Cheng

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/76807

摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

摘要翻译： 在半导体器件布置中形成双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。 在第一低k电介质层上形成氧化物蚀刻停止层，在氧化物蚀刻停止层上形成第二低k电介质层。 将通孔蚀刻到第一低k电介质层中，然后将沟槽蚀刻到第二低k电介质层中。 第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 因此，在蚀刻第二介质层中沟槽的过程中，通过采用只刻蚀第二低k电介质材料而不是第一低k电介质材料的蚀刻化学法来防止第一介质层中的底切。

公开(公告)号：US6107208A

公开(公告)日：2000-08-22

申请号：US90670

申请日：1998-06-04

申请人： Jerry Cheng ,  Fei Wang

发明人： Jerry Cheng ,  Fei Wang

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L21/05

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/76829 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002

摘要： In one embodiment, the present invention relates to a method of etching silicon nitride disposed over a copper containing layer by etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising from about 5 sccm to about 15 sccm of CHF.sub.3, about 5 sccm to about 15 sccm of nitrogen and about 80 sccm to about 120 sccm of a carrier gas. In another embodiment, the present invention relates to a method of processing a semiconductor substrate comprising silicon nitride disposed over a copper containing layer, involving etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising CHF.sub.3, nitrogen and Ar.

摘要翻译： 在一个实施例中，本发明涉及一种通过使用包含约5sccm至约15sccm的CHF 3的氮化物蚀刻气体混合物蚀刻至少一部分氮化硅而蚀刻设置在含铜层上方的氮化硅的方法，约 5sccm至约15sccm的氮气和约80sccm至约120sccm的载气。 在另一个实施例中，本发明涉及一种处理半导体衬底的方法，该半导体衬底包括设置在含铜层上的氮化硅，包括使用包含CHF 3，氮和Ar的氮化物蚀刻气体混合物蚀刻至少一部分氮化硅。

公开(公告)号：US6086777A

公开(公告)日：2000-07-11

申请号：US108783

申请日：1998-07-02

申请人： Jerry Cheng ,  Fei Wang

发明人： Jerry Cheng ,  Fei Wang

IPC分类号： C23F4/00 ,  H01L21/3213 ,  H01L21/768 ,  C23F1/10

CPC分类号： H01L21/7684 ,  C23F4/00 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76873

摘要： In one embodiment, the present invention relates to a method of etching tantalum disposed over a dielectric layer, involving etching at least a portion of the tantalum using a tantalum etch gas mixture containing from about 300 sccm to about 400 sccm of CF.sub.4 and about 200 sccm to about 600 sccm of oxygen at a temperature from about 100.degree. C. to about 150.degree. C. under a pressure from about 1 torr to about 1.5 torr. In another embodiment, the present invention relates to a method of etching at least a portion of a tantalum barrier layer, the tantalum barrier layer at least partially surrounding a copper or copper alloy interconnect, involving etching at least a portion of the tantalum barrier layer using a tantalum etch gas mixture containing from about 300 sccm to about 400 sccm of CF.sub.4 and about 200 sccm to about 600 sccm of oxygen.

摘要翻译： 在一个实施例中，本发明涉及蚀刻设置在电介质层上的钽的方法，包括使用包含约300sccm至约400sccm的CF 4和约200sccm的钽蚀刻气体混合物来蚀刻钽的至少一部分 至约600sccm的氧气，在约1托至约1.5托的压力下在约100℃至约150℃的温度下进行。 在另一个实施例中，本发明涉及一种蚀刻钽阻挡层的至少一部分的方法，所述钽阻挡层至少部分地围绕铜或铜合金互连，包括用钽蚀刻至少一部分钽阻挡层，使用 包含约300sccm至约400sccm的CF 4和约200sccm至约600sccm的氧的钽蚀刻气体混合物。

公开(公告)号：US06207576B1

公开(公告)日：2001-03-27

申请号：US09225543

申请日：1999-01-05

申请人： Fei Wang ,  Jerry Cheng

发明人： Fei Wang ,  Jerry Cheng

IPC分类号： H01L213065

CPC分类号： H01L21/7681 ,  H01L21/02118 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/312

摘要： A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A trench is etched into the second low k dielectric layer, followed by the etching of a via into the first low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the first low k dielectric material and not the second low k dielectric material.

摘要翻译： 在半导体器件布置中形成自对准双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。 在第一低k电介质层上形成氧化物蚀刻停止层，在氧化物蚀刻停止层上形成第二低k电介质层。 将沟槽蚀刻到第二低k介电层中，随后将通孔蚀刻到第一低k电介质层中。 第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 因此，在蚀刻第二介质层中的通孔时，通过采用蚀刻仅仅第一低k电介质材料而不是第二低k电介质材料的蚀刻化学法，由此防止了由过蚀刻引起的第二电介质层中的底切。

公开(公告)号：US06756300B1

公开(公告)日：2004-06-29

申请号：US10324259

申请日：2002-12-18

申请人： Fei Wang ,  Jerry Cheng ,  Lynne A. Okada ,  Minh Quoc Tran ,  Lu You

发明人： Fei Wang ,  Jerry Cheng ,  Lynne A. Okada ,  Minh Quoc Tran ,  Lu You

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/76813

摘要： For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.

摘要翻译： 为了在介电材料内形成双镶嵌开口，在电介质材料上形成通孔掩模材料和沟槽掩模材料。 通过沟槽掩模材料形成沟槽开口，并且通过布置在通孔和沟槽掩模材料上方的通孔掩模图案形成材料形成通孔开口。 通过通孔掩模图形材料的通路孔露出的通孔和沟槽掩模材料被蚀刻掉，并且通孔掩模图案材料被蚀刻掉。 通过通孔开口暴露的介电材料的一部分被蚀刻到下面的互连结构上，并且蚀刻通过沟槽开口露出的电介质材料的一部分，以形成双镶嵌开口。

公开(公告)号：US06472317B1

公开(公告)日：2002-10-29

申请号：US09780457

申请日：2001-02-12

申请人： Fei Wang ,  Jerry Cheng ,  Simon S. Chan ,  Todd Lukanc

发明人： Fei Wang ,  Jerry Cheng ,  Simon S. Chan ,  Todd Lukanc

IPC分类号： H01L214763

CPC分类号： H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A second low k dielectric layer is formed on the first low k dielectric layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Further etching of the first dielectric layer is prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

摘要翻译： 在半导体器件布置中形成双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。 在第一低k电介质层上形成第二低k电介质层。 将通孔蚀刻到第一低k电介质层中，然后将沟槽蚀刻到第二低k电介质层中。 第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 在蚀刻第二电介质层中的沟槽期间，通过采用蚀刻仅蚀刻第二低k电介质材料而不是第一低k电介质材料的蚀刻化学品来防止第一电介质层的进一步腐蚀。

公开(公告)号：US06380091B1

公开(公告)日：2002-04-30

申请号：US09238050

申请日：1999-01-27

申请人： Fei Wang ,  Jerry Cheng ,  Darrell M. Erb

发明人： Fei Wang ,  Jerry Cheng ,  Darrell M. Erb

IPC分类号： H01L213065

CPC分类号： H01L21/76807 ,  H01L21/31116 ,  H01L2221/1036

摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first dielectric layer made of an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first dielectric layer, and a second dielectric layer, made of low k dielectric material, is formed on the nitride etch stop layer. A via is etched into the first dielectric layer, and a trench is then etched into the second dielectric layer. The materials if the first and second dielectric layers are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second dielectric layer and not the first dielectric layer.

摘要翻译： 在半导体器件布置中形成双镶嵌结构的方法在诸如铜互连层的下面的金属互连层上形成由氧化物介电材料制成的第一介电层。 在第一电介质层上形成氮化物蚀刻停止层，在氮化物蚀刻停止层上形成由低k电介质材料制成的第二电介质层。 将通孔蚀刻到第一介电层中，然后将沟槽蚀刻到第二介电层中。 如果第一和第二电介质层彼此不同，那么材料使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 因此，在蚀刻第二电介质层中的沟槽的过程中，通过采用只蚀刻第二电介质层而不是第一介电层的蚀刻化学法来防止在第一电介质层中的底切。

公开(公告)号：US06255735B1

公开(公告)日：2001-07-03

申请号：US09225542

申请日：1999-01-05

申请人： Fei Wang ,  Jerry Cheng ,  Simon S. Chan ,  Todd Lukanc

发明人： Fei Wang ,  Jerry Cheng ,  Simon S. Chan ,  Todd Lukanc

IPC分类号： H01L2348

CPC分类号： H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A second low k dielectric layer is formed on the first low k dielectric layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Further etching of the first dielectric layer is prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

摘要翻译： 在半导体器件布置中形成双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。 在第一低k电介质层上形成第二低k电介质层。 将通孔蚀刻到第一低k电介质层中，然后将沟槽蚀刻到第二低k电介质层中。 第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 在蚀刻第二电介质层中的沟槽期间，通过采用蚀刻仅蚀刻第二低k电介质材料而不是第一低k电介质材料的蚀刻化学品来防止第一电介质层的进一步腐蚀。

公开(公告)号：US06207577B1

公开(公告)日：2001-03-27

申请号：US09238049

申请日：1999-01-27

申请人： Fei Wang ,  Jerry Cheng ,  Darrell M. Erb

发明人： Fei Wang ,  Jerry Cheng ,  Darrell M. Erb

IPC分类号： H01L213065

CPC分类号： H01L21/7681 ,  H01L21/31138 ,  H01L2221/1036

摘要： A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the oxide dielectric layer, and a low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the low k dielectric layer, followed by the etching of a via into the oxide dielectric layer. The oxide dielectric material and low k dielectric material are selected so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the oxide dielectric material and not the low k dielectric material.

摘要翻译： 在半导体器件布置中形成自对准双镶嵌结构的方法在诸如铜互连层的下面的金属互连层之上形成氧化物介电材料。 在氧化物介电层上形成氮化物蚀刻停止层，在氮化物蚀刻停止层上形成低k电介质层。 将沟槽蚀刻到低k电介质层中，然后将通孔蚀刻到氧化物介电层中。 选择氧化物介电材料和低k电介质材料使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 因此，在蚀刻第二电介质层中的通孔时，通过采用仅蚀刻氧化物电介质材料而不是低k电介质材料的蚀刻化学品来防止由过蚀蚀引起的第二电介质层中的底切。

公开(公告)号：US06291887B1

公开(公告)日：2001-09-18

申请号：US09225220

申请日：1999-01-04

申请人： Fei Wang ,  Jerry Cheng ,  Todd Lukanc

发明人： Fei Wang ,  Jerry Cheng ,  Todd Lukanc

IPC分类号： H01L2348

CPC分类号： H01L21/76835 ,  H01L21/76807 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the nitride etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

摘要翻译： 在半导体器件布置中形成双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。 在第一低k电介质层上形成氮化物蚀刻停止层，在氮化物蚀刻停止层上形成第二低k电介质层。 将通孔蚀刻到第一低k电介质层中，然后将沟槽蚀刻到第二低k电介质层中。 第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 因此，在蚀刻第二介质层中沟槽的过程中，通过采用只刻蚀第二低k电介质材料而不是第一低k电介质材料的蚀刻化学法来防止第一介质层中的底切。