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11 条记录 (耗时 0.059 秒)

    Automatic adjustment of the quantity of prefetch data in a disk cache operation
    2.
    发明授权
    Automatic adjustment of the quantity of prefetch data in a disk cache operation 失效
    在磁盘缓存操作中自动调整预取数据量

    公开(公告)号：US4489378A

    公开(公告)日：1984-12-18

    申请号：US270750

    申请日：1981-06-05

    申请人： Jerry D. Dixon ,  Gerald A. Marazas ,  Andrew B. McNeill ,  Gerald U. Merckel

    发明人： Jerry D. Dixon ,  Gerald A. Marazas ,  Andrew B. McNeill ,  Gerald U. Merckel

    IPC分类号： G06F12/08 ,  G06F13/12 ,  G06F9/06 ,  G06F13/00

    CPC分类号： G06F12/0862 ,  G06F13/122 ,  G06F12/0866 ,  G06F2212/502

    摘要： When transferring data to a cache memory from an attachment data storage device, additional unrequested information can be transferred at the same time if it is likely that this additional data will soon be requested. The average quantity of data transferred to the cache memory in each operation can be automatically and continually varied in order to maximize the performance advantage provided by the cache memory. When a record of data is requested by the host processor, data is transferred to the cache memory from an attachment data storage device in increments of fixed-length data blocks each containing a sequence of data records, with the number of transferred blocks being determined by the position of a requested data record in its respective data block, and the average number of blocks transferred in any one operation being varied by adjusting threshold position values at which second or third data blocks are transferred.

    摘要翻译： 当从附件数据存储设备传送数据到高速缓冲存储器时，如果很可能要求这个附加数据，则可以同时传送额外的未请求的信息。 在每个操作中传输到高速缓冲存储器的数据的平均数量可以被自动地和连续地变化，以便最大化缓存存储器提供的性能优势。 当主处理器请求数据记录时，数据以固定长度的数据块的增量从附件数据存储设备传送到高速缓冲存储器，每个固定长度数据块包含一系列数据记录，传送块的数量由 通过调整传送第二或第三数据块的阈值位置值来改变在其各自的数据块中所请求的数据记录的位置以及在任何一个操作中传送的块的平均数量。

    I/O Storage controller cache system with prefetch determined by requested record's position within data block
    4.
    发明授权
    I/O Storage controller cache system with prefetch determined by requested record's position within data block 失效
    具有预取的I / O存储控制器缓存系统由所请求的记录在数据块内的位置确定

    公开(公告)号：US4490782A

    公开(公告)日：1984-12-25

    申请号：US270951

    申请日：1981-06-05

    申请人： Jerry D. Dixon ,  Gerald A. Marazas ,  Gerald U. Merckel

    发明人： Jerry D. Dixon ,  Gerald A. Marazas ,  Gerald U. Merckel

    IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F13/12 ,  G06F9/06

    CPC分类号： G06F12/0862 ,  G06F13/122 ,  G06F12/0866 ,  G06F2212/502

    摘要： In a data processing system of the type wherein a host processor transfers data to or from a plurality of attachment devices, a cache memory is provided for storing blocks of data which are most likely to be needed by the host processor in the near future. The host processor can then merely retrieve the necessary information from the cache memory without the necessity of accessing the attachment devices. When transferring data to cache from an attachment disk, additional unrequested information can be transferred at the same time if it is likely that this additional data will soon be requested. Further, a directory table is maintained wherein all data in cache is listed at a "home" position and, if more than one block of data in cache have the same home position, a conflict chain is set-up so that checking the contents of the cache can be done simply and quickly.

    摘要翻译： 在其中主机处理器向多个附接装置传送数据或从多个附件装置传送数据的数据处理系统中，提供高速缓冲存储器用于存储在不久的将来最可能由主机处理器需要的数据块。 然后，主机处理器可以仅从高速缓存存储器中检索必要的信息，而无需访问附件设备。 从附件磁盘传输数据到缓存时，如果很可能要求这个附加数据可能会同时传输附加的未请求的信息。 此外，保持目录表，其中高速缓存中的所有数据都列在“本地”位置，并且如果高速缓存中的多于一个数据块具有相同的原始位置，则建立冲突链，以便检查 缓存可以简单而快速地完成。

    Method of handling disk sector errors in DASD cache
    6.
    发明授权
    Method of handling disk sector errors in DASD cache 失效
    在DASD缓存中处理磁盘扇区错误的方法

    公开(公告)号：US4972316A

    公开(公告)日：1990-11-20

    申请号：US32214

    申请日：1987-03-30

    申请人： Jerry D. Dixon ,  Guy G. Sotomayor, Jr.

    发明人： Jerry D. Dixon ,  Guy G. Sotomayor, Jr.

    IPC分类号： G06F3/06 ,  G06F12/08 ,  G06F12/16 ,  G11B20/18

    CPC分类号： G11B20/1816 ,  G06F12/0866 ,  G11B20/18

    摘要： In a DASD caching system, in which pages of sectors of data are stored by reading in a desired sector and prefetching a plurality of adjacent sectors for later access, errors in disk storage media cause error signals to be generated. Such errors are handled by storing indications of which sectors have errors and which do not, and accessing such indications in response to later requests for such sectors. Such indications are stored in each page in the cache. Further, a history is maintained of which pages and sectors therein, were placed in the cache in the past.

    Data processor input/output controller
    7.
    发明授权
    Data processor input/output controller 失效
    数据处理器输入/输出控制器

    公开(公告)号：US4246637A

    公开(公告)日：1981-01-20

    申请号：US919107

    申请日：1978-06-26

    申请人： Lewis W. Brown ,  Douglas R. Chisholm ,  Jerry D. Dixon

    发明人： Lewis W. Brown ,  Douglas R. Chisholm ,  Jerry D. Dixon

    IPC分类号： G06F13/12 ,  G06F13/32 ,  G06F3/00 ,  G06F9/22 ,  G06F15/16

    CPC分类号： G06F13/32

    摘要： A data processor input/output controller which is particularly useful as a microcontroller for the transfer of data between a host processor and one or more peripheral input/output devices in a digital data processing system. This input/output (I/O) controller is a subchannel controller for offloading a goodly portion of the subchannel control function from the host processor. This I/O controller includes a microprocessor for assisting and supervising the controller internal operations. Also included in the controller is an automatic high-speed data bypass mechanism whereby data may be transferred from the host processor to the I/O device or vice versa without having to pass through the microprocessor and without requiring any intervention on the part of the microprocessor during such automatic transfer. Provision is made for enabling the microprocessor to perform other functions, such as the presentation of interrupts to the host processor and the servicing of additional I/O commands from the host processor concurrently with the transfer of data via the automatic bypass mechanism. This capability is particularly useful where two or more I/O devices are connected to the controller. The automatic bypass mechanism is constructed to communicate with the host processor in a cycle steal mode. A look-ahead mechanism is provided for more quickly issuing the cycle steal requests to the host processor when operating in the automatic bypass mode.

    摘要翻译： 一种数据处理器输入/输出控制器，其特别用作用于在主处理器与数字数据处理系统中的一个或多个外围输入/输出设备之间传送数据的微控制器。 该输入/输出（I / O）控制器是用于从主处理器卸载子通道控制功能的很好部分的子通道控制器。 该I / O控制器包括用于辅助和监督控制器内部操作的微处理器。 还包括在控制器中的是一种自动高速数据旁路机制，其中数据可以从主机处理器传送到I / O设备，反之亦然，而不必通过微处理器而不需要微处理器的任何干预 在这种自动转移过程中。 提供了使微处理器能够执行其他功能，例如向主机处理器呈现中断，以及通过自动旁路机制与主机处理器同时传送数据的附加I / O命令的服务。 当两个或多个I / O设备连接到控制器时，此功能特别有用。 自动旁路机构被构造成以循环窃取模式与主机处理器进行通信。 提供了一种提前机制，用于在以自动旁路模式操作时更快地向主机处理器发出周期窃取请求。

    Paging mechanism
    8.
    发明授权
    Paging mechanism 失效
    寻呼机制

    公开(公告)号：US4218741A

    公开(公告)日：1980-08-19

    申请号：US918221

    申请日：1978-06-23

    申请人： Jerry D. Dixon ,  Joel C. Leininger

    发明人： Jerry D. Dixon ,  Joel C. Leininger

    IPC分类号： G06F12/06 ,  G06F9/32 ,  G06F9/34 ,  G06F9/355 ,  G06F9/40 ,  G06F12/02 ,  G06F9/20

    CPC分类号： G06F9/342 ,  G06F9/32 ,  G06F9/34

    摘要： In a data processing system, a mechanism provides independent assignment of page locations for a program's instructions and its data and better enables control to be transferred between programs, or portions thereof, that reside at different addresses in different pages of a multiple page instruction store. The initial linkage is established through the use of a Branch And Link instruction. Subsequent linkages are established through the use of Return and Link instructions, each of which transfers control to a previous program, or program segment, while simultaneously establishing the linkage for a subsequent return to this program or program segment.INTRODUCTIONCROSS REFERENCES TO RELATED APPLICATIONSU.S. Patent application of J. D. Dixon, one of the co-inventors herein, Ser. Nos. 866,425, filed Jan. 3, 1978 and 918,223, filed of even date herewith, both assigned to the assignee of the present invention, show and describe, but do not claim, portions of the invention claimed in the present invention.BACKGROUND OF THE INVENTIONThis invention relates to mechanisms for permitting program instructions and data to reside in the same or different pages of storage independently of each other and for facilitating communication between programs, or program segments, in different pages within a data processing system. More particularly, it relates to such a mechanism that is particularly useful in a small microprogrammed controller with insufficient address fields to access all of the storage which it is desired to utilize. An example of this type of small controller is shown and described at pages 3270-3273 of the Technical Disclosure Bulletin, Vol. 19 No. 9, published February, 1977 by the International Business Machines Corporation.The present invention is particularly useful in a microprocessor (or microcontroller) specifically adapted for control of I/O (input-output) devices. In such a controller maximum speed of operation, minimum cycle time is desirable. To optimize cycle time, all instructions are fixed at one processor cycle time--multiple fetches are not permitted. No address calculation is permitted.With these restrictions, paging is required to access memory larger than that defined by the maximum address structure in an instruction. Hardware paging is required for efficient instruction branches from one page to another.Paging mechanisms are known in the art and are often incorporated in processors where the maximum number of bits in the processor's address structure is insufficient to directly address all of the storage which is required for a particular application.Examples of paging structures are shown and described in the Technical Disclosure Bulletin, Volume 19 No. 8, pages 2877, 2878, and Volume 19, No. 9, pages 3266, 3267, published Jan. 1977 and February 1977 respectively, by International Business Machines Corporation.However, to the best of applicant's knowledge, no paging mechanism has been suggested which uses separate page registers, dynamically changeable under program control, for a program's instructions and its data so that the data may reside in the same page as, or a different page, than the instructions, independent of the instructions. With a minimum of hardware and software support, significant paging flexibility is achieved.In the preferred embodiment, the invention is incorporated in a micro-controller in which the instruction fetch and execute functions are overlapped. During the execution of one instruction, the next instruction is being fetched from memory. Care must be taken therefore in Branch and Link Type instructions to assure storing of the correct D/I bits with the current program instruction address bits.In a data processing system, particularly that part of a system which is used as a controller for, for example, a plurality of input/output (I/O) devices, it may be necessary for the system to execute separate control programs substantially concurrently even though they may run at asynchronous rates. In order to accomplish this, there must be a mechanism for transferring control between the two programs.A well known mechanism for accomplishing interaction between programs depends upon a hardware register which preserves, for a limited time, an indication of the memory address of an instruction in a program from which control was transferred. That instruction would typically be a (conditional or unconditional) branch instruction. If there would be a need to return control back to the original program, the contents of this register would have to be saved for subsequent utilization in returning. The saving of the contents of this register used storage (for the save instruction) and time (for the execution of the instruction) while accomplishing no other useful work.Some of the disadvantages of the system described above were overcome in the 1960's by the provision of a computer instruction called "Branch And Link". This instruction was implemented by hardware which, in response to the instruction, caused a branch to a particular address specified by the instruction, and automatically stored in a "link register" an indication of the address from which control was transferred. Subsequently, the execution of another instruction called "Return" would cause control to be transferred to the instruction at the address indicated by the link register. Thus, a programmer was able very easily to cause the exiting from a main stream of coding to a sub-routine, and then return to the main stream, by using two simple instructions with no need to concern himself with storing the contents of any particular registers.The improved paging structure of the present application must interact efficiently during these Branch and Link and Return instructions.SUMMARY OF THE INVENTIONIn the preferred embodiment, a novel paging mechanism is provided for efficient, yet flexible processor operation. A first hardware register I is provided to store the number (address) of the page in which the next instruction of the current program is stored and a second hardware register D stores the number of the page in which the next selected data for that program resides. By the use of Set Data Page (Set D) and Set Instruction Page (SI) instructions, the page numbers in the D/I registers can be changed at will by the programmer to achieve maximum flexibility in locating instructions and data.During instruction fetches, the I register contents are gated to a page decode circuit for selecting the page in which the instruction resides. At the same time, the offset address within the page is gated to a storage address register SAR to select the instruction location within the selected page.During data load and store operations the D register contents are gated to the page decode circuit to select the page in which the data resides; and the offset address within the page is gated to the SAR to fetch or store the desired data.The controller of the preferred embodiment has an overlapped instruction fetch/execution mode of operation. The formation of the address of the next instruction must therefore occur in the early part of the processor cycle. If, during a Set Instruction Page (SI) Instruction, the I register were set to the new page value and then the value were gated to the select circuit concurrent with setting the next address offset bits in the SAR, the SI instruction would in effect cause a branch to the new page; and, because the only offset address bits available are those in the SAR, the branched to address could only be that one offset address in the new page. This results in serious inflexibility.Hence, in the preferred form of the invention, the setting of the I register is delayed until the next instruction fetch is made, which fetch uses the old I bit. This causes fetching of the next sequential instruction after the SI instruction. This next instruction is one of the various Branch type instructions and includes within its branch address field the offset address of the branched to instruction in the new page defined by the new bit in the I register.A Set Data Page Instruction similarly sets the D register late in the execution cycle so that the old page value can be saved in the Link Register if a Branch and Link Instruction follows the Set Data Page Instruction.Another problem arises for the Branch and Link instructions which set the Link Register from the IAR register. For example, during a Branch and Link (BAL) Instruction which follows a SI instruction, the old D/I bits (prior to setting a new I bit in the I register) must be stored in the Link Register during the execution of the BAL instruction. However, during the preceding SI execution the old I bit was destroyed.Hence, in the preferred embodiment of the invention, a Delay register is interposed between the D/I registers and the Link Register. During each instruction execution, the contents of the D/I registers are gated into the Delay register. Upon occurrence of a branch and link instruction, the contents of the Delay Register will contain the old value of the D/I registers. As a result, the old D/I page values are available for storing in the link register whenever a new page value has been set (Set I or Set D) in the instruction cycle immediately preceding a Branch and Link type of instruction.

    摘要翻译： 在数据处理系统中，机构为程序的指令及其数据提供页面位置的独立分配，并且更好地使得能够在位于多页指令存储器的不同页面中的不同地址的程序或其部分之间传送控制。 通过使用分支和链接指令来建立初始链接。 后续联系通过使用Return和Link指令来建立，每个指令将控制权转移到以前的程序或程序段，同时建立连接以便后续返回此程序或程序段。

    Serial storage interface apparatus for coupling a serial storage mechanism to a data processor input/output bus
    9.
    发明授权
    Serial storage interface apparatus for coupling a serial storage mechanism to a data processor input/output bus 失效
    用于将串行存储机构耦合到数据处理器输入/输出总线的串行存储接口装置

    公开(公告)号：US4344132A

    公开(公告)日：1982-08-10

    申请号：US103782

    申请日：1979-12-14

    申请人： Jerry D. Dixon ,  Robert H. Farrell ,  Francis R. Koperda

    发明人： Jerry D. Dixon ,  Robert H. Farrell ,  Francis R. Koperda

    IPC分类号： G06F3/06 ,  G06F3/00 ,  G06F5/06

    CPC分类号： G06F5/06 ,  G06F3/007 ,  G06F2205/061

    摘要： Serial storage interface apparatus for coupling a serial storage mechanism, such as a charge coupled storage device or a magnetic bubble storage device, to a data processor input/output (I/O) bus. Speed control circuitry is provided for causing the serial storage mechanism to operate at a higher speed when the data processor is responding more rapidly to data transfer requests from the interface apparatus and at a lower speed when the data processor is responding less rapidly to data transfer requests from the interface apparatus. This speed adjustment feature reduces the amount of data buffering required for interfacing a serial storage mechanism to an asynchronous variable response time I/O bus system.

    摘要翻译： 用于将诸如电荷耦合存储装置或磁性气泡存储装置的串行存储机构耦合到数据处理器输入/输出（I / O）总线的串行存储接口装置。 提供速度控制电路，用于当数据处理器对数据处理器对数据传输请求的响应不太快时，数据处理器对来自接口装置的数据传输请求作出更快的响应并以较低的速度响应时，使串行存储机构以更高的速度运行 从接口装置。 这种速度调节功能减少了将串行存储机制连接到异步可变响应时间I / O总线系统所需的数据缓冲量。

    Return and link mechanism
    10.
    发明授权
    Return and link mechanism 失效
    返回和链接机制

    公开(公告)号：US4173782A

    公开(公告)日：1979-11-06

    申请号：US866425

    申请日：1978-01-03

    申请人： Jerry D. Dixon

    发明人： Jerry D. Dixon

    IPC分类号： G06F9/46 ,  G06F9/40 ,  G06F9/42 ,  G06F9/18

    CPC分类号： G06F9/4426

    摘要： In a data processing system, a mechanism for enabling control to be transferred between programs, or portions thereof, that reside at different addresses in an instruction store. The initial linkage is established through the use of a Branch And Link instruction. Subsequent linkages are established through the use of Return And Link instructions, each of which causes the mechanism to transfer control to a previous program, or program segment, while simultaneously establishing the linkage for a subsequent return to this program or program segment.

    摘要翻译： 在数据处理系统中，用于使得能够在驻留在指令存储器中的不同地址的程序或其部分之间传送控制的机制。 通过使用分支和链接指令来建立初始链接。 后续链接通过使用Return and Link指令建立，每个指令都使机制将控制转移到先前的程序或程序段，同时建立连接以便后续返回到该程序或程序段。