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公开(公告)号：US20080086622A1
公开(公告)日：2008-04-10
申请号：US11546223
申请日：2006-10-10
申请人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
发明人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
IPC分类号： G06F9/30
CPC分类号： G06F9/3842
摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.
摘要翻译： 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于所识别的该子集的重放情况为止的确认指示为止。
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公开(公告)号：US08255670B2
公开(公告)日：2012-08-28
申请号：US12619751
申请日：2009-11-17
申请人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
发明人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
CPC分类号： G06F9/3842
摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.
摘要翻译： 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于该子集的所识别的重放大小写的确认指示为止。
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公开(公告)号：US20070106874A1
公开(公告)日：2007-05-10
申请号：US11267711
申请日：2005-11-04
申请人： Jesse Pan , Ramesh Gunna
发明人： Jesse Pan , Ramesh Gunna
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F12/1072 , G06F12/124
摘要： In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.
摘要翻译： 在一个实施例中，处理器包括存储器管理单元（MMU）和耦合到MMU和处理器的接口单元的接口单元。 MMU包括被配置为存储未决硬件生成的页表项（PTE）更新的队列。 接口单元被配置为在接口上接收同步操作，所述同步操作被定义为使未决的硬件产生的PTE更新（如果有的话）被写入存储器。 MMU配置为接受在接收同步操作之后生成的后续硬件生成的PTE更新，即使同步操作在接口上尚未完成。 在一些实施例中，MMU可以响应于从队列发送未决PTE更新来接受后续PTE更新。 在其他实施例中，可以在队列中识别未决PTE更新，并且可以接收后续更新。
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公开(公告)号：US08341379B2
公开(公告)日：2012-12-25
申请号：US12774389
申请日：2010-05-05
申请人： Jesse Pan , Ramesh Gunna
发明人： Jesse Pan , Ramesh Gunna
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F12/1072 , G06F12/124
摘要： In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.
摘要翻译： 在一个实施例中，处理器包括存储器管理单元（MMU）和耦合到MMU和处理器的接口单元的接口单元。 MMU包括被配置为存储未决硬件生成的页表项（PTE）更新的队列。 接口单元被配置为在接口上接收同步操作，所述同步操作被定义为使未决的硬件产生的PTE更新（如果有的话）被写入存储器。 MMU配置为接受在接收同步操作之后生成的后续硬件生成的PTE更新，即使同步操作在接口上尚未完成。 在一些实施例中，MMU可以响应于从队列发送未决PTE更新来接受后续PTE更新。 在其他实施例中，可以在队列中识别未决PTE更新，并且可以接收后续更新。
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公开(公告)号：US07739476B2
公开(公告)日：2010-06-15
申请号：US11267711
申请日：2005-11-04
申请人： Jesse Pan , Ramesh Gunna
发明人： Jesse Pan , Ramesh Gunna
IPC分类号： G06F12/00 , G06F12/10 , G06F15/16 , G06F15/177
CPC分类号： G06F12/10 , G06F12/1072 , G06F12/124
摘要： In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.
摘要翻译： 在一个实施例中，处理器包括存储器管理单元（MMU）和耦合到MMU和处理器的接口单元的接口单元。 MMU包括被配置为存储未决硬件生成的页表项（PTE）更新的队列。 接口单元被配置为在接口上接收同步操作，所述同步操作被定义为使未决的硬件产生的PTE更新（如果有的话）被写入存储器。 MMU配置为接受在接收同步操作之后生成的后续硬件生成的PTE更新，即使同步操作在接口上尚未完成。 在一些实施例中，MMU可以响应于从队列发送未决PTE更新来接受后续PTE更新。 在其他实施例中，可以在队列中识别未决PTE更新，并且可以接收后续更新。
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公开(公告)号：US20100217951A1
公开(公告)日：2010-08-26
申请号：US12774389
申请日：2010-05-05
申请人： Jesse Pan , Ramesh Gunna
发明人： Jesse Pan , Ramesh Gunna
CPC分类号： G06F12/10 , G06F12/1072 , G06F12/124
摘要： In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.
摘要翻译： 在一个实施例中，处理器包括存储器管理单元（MMU）和耦合到MMU和处理器的接口单元的接口单元。 MMU包括被配置为存储未决硬件生成的页表项（PTE）更新的队列。 接口单元被配置为在接口上接收同步操作，所述同步操作被定义为使未决的硬件产生的PTE更新（如果有的话）被写入存储器。 MMU配置为接受在接收同步操作之后生成的后续硬件生成的PTE更新，即使同步操作在接口上尚未完成。 在一些实施例中，MMU可以响应于从队列发送未决PTE更新来接受后续PTE更新。 在其他实施例中，可以在队列中识别未决PTE更新，并且可以接收后续更新。
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公开(公告)号：US20100064120A1
公开(公告)日：2010-03-11
申请号：US12619751
申请日：2009-11-17
申请人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
发明人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
IPC分类号： G06F9/30
CPC分类号： G06F9/3842
摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.
摘要翻译： 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于该子集的所识别的重放大小写的确认指示为止。
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公开(公告)号：US07647518B2
公开(公告)日：2010-01-12
申请号：US11546223
申请日：2006-10-10
申请人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
发明人： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
CPC分类号： G06F9/3842
摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.
摘要翻译： 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于所识别的该子集的重放情况为止的确认指示为止。
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公开(公告)号：US20130103923A1
公开(公告)日：2013-04-25
申请号：US13277793
申请日：2011-10-20
申请人： Jesse Pan
发明人： Jesse Pan
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/654 , G06F2212/684
摘要： A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available translation-lookaside-buffer (TLB). The MMU determines whether a memory access operation associated with the given virtual address is the oldest, uncompleted memory access operation in a scheduler. If this is the case, a demand table walk (TW) request may be stored in an available entry in a TW queue. During this time, the utilization of the memory subsystem resources may be low. While a demand TW request is stored in the TW queue, subsequent speculative TW requests may be stored in the TW queue. When the TW queue does not store a demand TW request, no more entries of the TW queue may be allocated to store TW requests.
摘要翻译： 有效处理翻译后备缓冲（TLB）的系统和方法未命中。 存储器管理单元（MMU）检测每个可用的翻译 - 后备缓冲器（TLB）中的给定虚拟地址何时丢失。 MMU确定与给定虚拟地址相关联的存储器访问操作是否是调度器中最旧的未完成的存储器访问操作。 如果是这种情况，可以在TW队列中的可用条目中存储请求表行进（TW）请求。 在此期间，内存子系统资源的利用可能很低。 当TW请求存储在TW队列中时，随后的推测TW请求可以存储在TW队列中。 当TW队列不存储请求TW请求时，不再分配TW队列的更多条目来存储TW请求。
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公开(公告)号：US09009445B2
公开(公告)日：2015-04-14
申请号：US13277793
申请日：2011-10-20
申请人： Jesse Pan
发明人： Jesse Pan
CPC分类号： G06F12/1027 , G06F2212/654 , G06F2212/684
摘要： A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available translation-lookaside-buffer (TLB). The MMU determines whether a memory access operation associated with the given virtual address is the oldest, uncompleted memory access operation in a scheduler. If this is the case, a demand table walk (TW) request may be stored in an available entry in a TW queue. During this time, the utilization of the memory subsystem resources may be low. While a demand TW request is stored in the TW queue, subsequent speculative TW requests may be stored in the TW queue. When the TW queue does not store a demand TW request, no more entries of the TW queue may be allocated to store TW requests.
摘要翻译： 有效处理翻译后备缓冲（TLB）的系统和方法未命中。 存储器管理单元（MMU）检测每个可用的翻译 - 后备缓冲器（TLB）中的给定虚拟地址何时丢失。 MMU确定与给定虚拟地址相关联的存储器访问操作是否是调度器中最旧的未完成的存储器访问操作。 如果是这种情况，可以在TW队列中的可用条目中存储请求表行进（TW）请求。 在此期间，内存子系统资源的利用可能很低。 当TW请求存储在TW队列中时，随后的推测TW请求可以存储在TW队列中。 当TW队列不存储请求TW请求时，不再分配TW队列的更多条目来存储TW请求。
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