公开(公告)号：US20080086622A1

公开(公告)日：2008-04-10

申请号：US11546223

申请日：2006-10-10

申请人： Po-Yung Chang ,  Wei-Han Lien ,  Jesse Pan ,  Ramesh Gunna ,  Tse-Yu Yeh ,  James B. Keller

发明人： Po-Yung Chang ,  Wei-Han Lien ,  Jesse Pan ,  Ramesh Gunna ,  Tse-Yu Yeh ,  James B. Keller

IPC分类号： G06F9/30

CPC分类号： G06F9/3842

摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.

摘要翻译： 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于所识别的该子集的重放情况为止的确认指示为止。

公开(公告)号：US08255670B2

公开(公告)日：2012-08-28

申请号：US12619751

申请日：2009-11-17

申请人： Po-Yung Chang ,  Wei-Han Lien ,  Jesse Pan ,  Ramesh Gunna ,  Tse-Yu Yeh ,  James B. Keller

发明人： Po-Yung Chang ,  Wei-Han Lien ,  Jesse Pan ,  Ramesh Gunna ,  Tse-Yu Yeh ,  James B. Keller

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3842

摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.

摘要翻译： 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于该子集的所识别的重放大小写的确认指示为止。

公开(公告)号：US20070106874A1

公开(公告)日：2007-05-10

申请号：US11267711

申请日：2005-11-04

申请人： Jesse Pan ,  Ramesh Gunna

发明人： Jesse Pan ,  Ramesh Gunna

IPC分类号： G06F12/00

CPC分类号： G06F12/10 ,  G06F12/1072 ,  G06F12/124

摘要： In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.

摘要翻译： 在一个实施例中，处理器包括存储器管理单元（MMU）和耦合到MMU和处理器的接口单元的接口单元。 MMU包括被配置为存储未决硬件生成的页表项（PTE）更新的队列。 接口单元被配置为在接口上接收同步操作，所述同步操作被定义为使未决的硬件产生的PTE更新（如果有的话）被写入存储器。 MMU配置为接受在接收同步操作之后生成的后续硬件生成的PTE更新，即使同步操作在接口上尚未完成。 在一些实施例中，MMU可以响应于从队列发送未决PTE更新来接受后续PTE更新。 在其他实施例中，可以在队列中识别未决PTE更新，并且可以接收后续更新。

公开(公告)号：US08341379B2

公开(公告)日：2012-12-25

申请号：US12774389

申请日：2010-05-05

申请人： Jesse Pan ,  Ramesh Gunna

发明人： Jesse Pan ,  Ramesh Gunna

IPC分类号： G06F12/00

CPC分类号： G06F12/10 ,  G06F12/1072 ,  G06F12/124

摘要： In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.

摘要翻译： 在一个实施例中，处理器包括存储器管理单元（MMU）和耦合到MMU和处理器的接口单元的接口单元。 MMU包括被配置为存储未决硬件生成的页表项（PTE）更新的队列。 接口单元被配置为在接口上接收同步操作，所述同步操作被定义为使未决的硬件产生的PTE更新（如果有的话）被写入存储器。 MMU配置为接受在接收同步操作之后生成的后续硬件生成的PTE更新，即使同步操作在接口上尚未完成。 在一些实施例中，MMU可以响应于从队列发送未决PTE更新来接受后续PTE更新。 在其他实施例中，可以在队列中识别未决PTE更新，并且可以接收后续更新。

公开(公告)号：US07739476B2

公开(公告)日：2010-06-15

申请号：US11267711

申请日：2005-11-04

申请人： Jesse Pan ,  Ramesh Gunna

发明人： Jesse Pan ,  Ramesh Gunna

IPC分类号： G06F12/00 ,  G06F12/10 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F12/10 ,  G06F12/1072 ,  G06F12/124

摘要： In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.

摘要翻译： 在一个实施例中，处理器包括存储器管理单元（MMU）和耦合到MMU和处理器的接口单元的接口单元。 MMU包括被配置为存储未决硬件生成的页表项（PTE）更新的队列。 接口单元被配置为在接口上接收同步操作，所述同步操作被定义为使未决的硬件产生的PTE更新（如果有的话）被写入存储器。 MMU配置为接受在接收同步操作之后生成的后续硬件生成的PTE更新，即使同步操作在接口上尚未完成。 在一些实施例中，MMU可以响应于从队列发送未决PTE更新来接受后续PTE更新。 在其他实施例中，可以在队列中识别未决PTE更新，并且可以接收后续更新。

公开(公告)号：US20100217951A1

公开(公告)日：2010-08-26

申请号：US12774389

申请日：2010-05-05

申请人： Jesse Pan ,  Ramesh Gunna

发明人： Jesse Pan ,  Ramesh Gunna

IPC分类号： G06F12/10 ,  G06F13/00 ,  G06F9/46

CPC分类号： G06F12/10 ,  G06F12/1072 ,  G06F12/124

摘要： In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.

摘要翻译： 在一个实施例中，处理器包括存储器管理单元（MMU）和耦合到MMU和处理器的接口单元的接口单元。 MMU包括被配置为存储未决硬件生成的页表项（PTE）更新的队列。 接口单元被配置为在接口上接收同步操作，所述同步操作被定义为使未决的硬件产生的PTE更新（如果有的话）被写入存储器。 MMU配置为接受在接收同步操作之后生成的后续硬件生成的PTE更新，即使同步操作在接口上尚未完成。 在一些实施例中，MMU可以响应于从队列发送未决PTE更新来接受后续PTE更新。 在其他实施例中，可以在队列中识别未决PTE更新，并且可以接收后续更新。

公开(公告)号：US20100064120A1

公开(公告)日：2010-03-11

申请号：US12619751

申请日：2009-11-17

申请人： Po-Yung Chang ,  Wei-Han Lien ,  Jesse Pan ,  Ramesh Gunna ,  Tse-Yu Yeh ,  James B. Keller

发明人： Po-Yung Chang ,  Wei-Han Lien ,  Jesse Pan ,  Ramesh Gunna ,  Tse-Yu Yeh ,  James B. Keller

IPC分类号： G06F9/30

CPC分类号： G06F9/3842

摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.

摘要翻译： 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于该子集的所识别的重放大小写的确认指示为止。

公开(公告)号：US07647518B2

公开(公告)日：2010-01-12

申请号：US11546223

申请日：2006-10-10

申请人： Po-Yung Chang ,  Wei-Han Lien ,  Jesse Pan ,  Ramesh Gunna ,  Tse-Yu Yeh ,  James B. Keller

发明人： Po-Yung Chang ,  Wei-Han Lien ,  Jesse Pan ,  Ramesh Gunna ,  Tse-Yu Yeh ,  James B. Keller

IPC分类号： G06F1/32 ,  G06F9/38

CPC分类号： G06F9/3842

摘要： In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.

摘要翻译： 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于所识别的该子集的重放情况为止的确认指示为止。

公开(公告)号：US08359414B2

公开(公告)日：2013-01-22

申请号：US13165235

申请日：2011-06-21

申请人： James B. Keller ,  Sridhar P. Subramanian ,  Ramesh Gunna

发明人： James B. Keller ,  Sridhar P. Subramanian ,  Ramesh Gunna

IPC分类号： G06F3/00 ,  G06F15/167

CPC分类号： G06F12/0831 ,  G06F13/362 ,  G06F13/4213 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.

摘要翻译： 接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。 在一个实施例中，控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。 控制单元被配置为记录在互连上提供的标识符，该重试响应标识互连上正在进行的第二事务。 控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。 在另一个实施例中，控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应 。 控制单元还被配置为提供具有重试响应的第二事务的标识符。

公开(公告)号：US08171326B2

公开(公告)日：2012-05-01

申请号：US12785842

申请日：2010-05-24

申请人： James B. Keller ,  Tse-Yu Yeh ,  Ramesh Gunna ,  Brian J. Campbell

发明人： James B. Keller ,  Tse-Yu Yeh ,  Ramesh Gunna ,  Brian J. Campbell

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D50/20

摘要： In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.

摘要翻译： 在一个实施例中，处理器包括被配置为存储多个高速缓存块的数据高速缓存和耦合到数据高速缓存的控制单元。 控制单元被配置为响应于处理器将转换到其中禁止用于处理器的一个或多个时钟的低功率状态的指示，从数据高速缓冲存储器中刷新多个高速缓存块。