公开(公告)号：US07587020B2

公开(公告)日：2009-09-08

申请号：US11739756

申请日：2007-04-25

申请人： Jethro C. Law ,  Trong V. Luong ,  Hung C. Ngo ,  Peter J. Klim

发明人： Jethro C. Law ,  Trong V. Luong ,  Hung C. Ngo ,  Peter J. Klim

IPC分类号： H03K25/00 ,  H03K23/50

CPC分类号： H03K23/40 ,  H03K21/026

摘要： A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.

摘要翻译： 提出了一个高性能，低功耗的上/下计数器。 提供的计数器由两个时钟脉冲，上升脉冲和下降脉冲控制，并并行更新计数器的所有位。 然后使用可扫描的脉冲限制输出开关动态逻辑锁存器锁存这些位。 通过使用有限开关动态逻辑锁存器，计数器能够利用动态逻辑的速度，而不需要传统的动态逻辑电源。 与典型的边沿触发触发器相比，通过使用动态锁存器保存的区域和速度是显着的。 此外，通过并行计算所有下一个计数状态位，计数器通过消除计数器纹波来减少总计数计算延迟。

公开(公告)号：US20080265957A1

公开(公告)日：2008-10-30

申请号：US11739760

申请日：2007-04-25

申请人： Trong V. Luong ,  Hung C. Ngo ,  Jethro C. Law ,  Peter J. Klim

发明人： Trong V. Luong ,  Hung C. Ngo ,  Jethro C. Law ,  Peter J. Klim

IPC分类号： H03L7/06

CPC分类号： H03L7/089

摘要： A phase detector which provides a dynamic output signal and which automatically resets if a reference clock signal and a feedback clock signal align after an output pulse is generated. With the phase detector in accordance with the present invention, when there is a difference between the positive clock edges of the reference clock signal and the feedback clock signal, the phase detector generates output pulse. The output is used to correct the feedback clock signal. In the next cycle, if the feedback signal is corrected so that both the reference clock signal and feedback clock signal are aligned, then the output signals are reset to zero. The ability to reset advantageously prevents an unexpected correction that can occur in certain phase detector designs.

摘要翻译： 相位检测器，其提供动态输出信号，并且如果在产生输出脉冲之后参考时钟信号和反馈时钟信号对准，则自动复位。 利用根据本发明的相位检测器，当参考时钟信号的正时钟沿与反馈时钟信号之间存在差异时，相位检测器产生输出脉冲。 输出用于校正反馈时钟信号。 在下一个周期中，如果反馈信号被校正，使得参考时钟信号和反馈时钟信号都对准，则输出信号被复位为零。 复位的能力有利地防止了在某些相位检测器设计中可能出现的意外的校正。

公开(公告)号：US20080267341A1

公开(公告)日：2008-10-30

申请号：US11739756

申请日：2007-04-25

申请人： Jethro C. Law ,  Trong V. Luong ,  Hung C. Ngo ,  Peter J. Klim

发明人： Jethro C. Law ,  Trong V. Luong ,  Hung C. Ngo ,  Peter J. Klim

IPC分类号： H03K25/00

CPC分类号： H03K23/40 ,  H03K21/026

摘要： A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.

摘要翻译： 提出了一个高性能，低功耗的上/下计数器。 提供的计数器由两个时钟脉冲，上升脉冲和下降脉冲控制，并并行更新计数器的所有位。 然后使用可扫描的脉冲限制输出开关动态逻辑锁存器锁存这些位。 通过使用有限开关动态逻辑锁存器，计数器能够利用动态逻辑的速度，而不需要传统的动态逻辑电源。 与典型的边沿触发触发器相比，通过使用动态锁存器保存的区域和速度是显着的。 此外，通过并行计算所有下一个计数状态位，计数器通过消除计数器纹波来减少总计数计算延迟。

公开(公告)号：US07557616B2

公开(公告)日：2009-07-07

申请号：US12172656

申请日：2008-07-14

申请人： Peter J. Klim ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Matthews

发明人： Peter J. Klim ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Matthews

IPC分类号： H03K19/00

CPC分类号： H03K19/0963

摘要： A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

摘要翻译： 具有有限开关动态逻辑门的电路，其具有前端逻辑电路和锁存器。 前端逻辑电路的输出连接到锁存器的输入，前端逻辑电路评估施加到前端逻辑电路的一组输入信号以产生输出信号。 锁存器接收并保持输出信号。 电路还具有逻辑电路，其输出端连接到前端逻辑电路中的时钟输入端。 逻辑电路响应于从时钟源接收时钟信号而产生修改的时钟信号，并且修改的时钟信号具有提供最小时间段的持续时间，用于前端逻辑以评估该组输入信号并产生 输出信号。

公开(公告)号：US20090108875A1

公开(公告)日：2009-04-30

申请号：US12174543

申请日：2008-07-16

申请人： Peter J. Klim ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Mathews

发明人： Peter J. Klim ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Mathews

IPC分类号： H03K19/096 ,  G06F17/50 ,  H03K19/00

CPC分类号： H03K19/0963

摘要： A design structure for a circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

摘要翻译： 具有具有前端逻辑电路和锁存器的有限开关动态逻辑门的电路的设计结构。 前端逻辑电路的输出连接到锁存器的输入，前端逻辑电路评估施加到前端逻辑电路的一组输入信号以产生输出信号。 锁存器接收并保持输出信号。 电路还具有逻辑电路，其输出端连接到前端逻辑电路中的时钟输入端。 逻辑电路响应于从时钟源接收时钟信号而产生修改的时钟信号，并且修改的时钟信号具有提供最小时间段的持续时间，用于前端逻辑以评估该组输入信号并产生 输出信号。

公开(公告)号：US20090108874A1

公开(公告)日：2009-04-30

申请号：US12172656

申请日：2008-07-14

申请人： Peter J. Klim ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Mathews

发明人： Peter J. Klim ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Mathews

IPC分类号： H03K19/096 ,  H03K19/00

CPC分类号： H03K19/0963

摘要： A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

摘要翻译： 具有有限开关动态逻辑门的电路，其具有前端逻辑电路和锁存器。 前端逻辑电路的输出连接到锁存器的输入，前端逻辑电路评估施加到前端逻辑电路的一组输入信号以产生输出信号。 锁存器接收并保持输出信号。 电路还具有逻辑电路，其输出端连接到前端逻辑电路中的时钟输入端。 逻辑电路响应于从时钟源接收时钟信号而产生修改的时钟信号，并且修改的时钟信号具有提供最小时间段的持续时间，用于前端逻辑以评估该组输入信号并产生 输出信号。

公开(公告)号：US07525393B2

公开(公告)日：2009-04-28

申请号：US11740612

申请日：2007-04-26

申请人： Hung C. Ngo ,  Fadi H. Gebara ,  Jethro C. Law ,  Trong V. Luong

发明人： Hung C. Ngo ,  Fadi H. Gebara ,  Jethro C. Law ,  Trong V. Luong

IPC分类号： H03L7/00

CPC分类号： H03L7/093 ,  H03L7/0991 ,  H03L7/18

摘要： A digital frequency multiplier circuit is disclosed. The digital frequency multiplier circuit includes a digitally controlled oscillator (DCO), a phase detector and a control circuit. The DCO generates an internal feedback signal. The phase detector detects a phase difference between the internal feedback signal and an external reference clock signal. Coupled between the phase detector and the DCO, the control circuit adjusts the DCO to align the internal feedback signal with the external reference clock signal after a phase difference between the internal feedback signal and the external reference clock signal has been detected. The control circuit also locks a modulation frequency of the DCO and monitors the state of the digital frequency multiplier circuit in order to maintain the lock.

摘要翻译： 公开了一种数字倍频器电路。 数字倍频器电路包括数字控制振荡器（DCO），相位检测器和控制电路。 DCO产生内部反馈信号。 相位检测器检测内部反馈信号和外部参考时钟信号之间的相位差。 在相位检测器和DCO之间耦合，在内部反馈信号和外部参考时钟信号之间的相位差被检测到之后，控制电路调节DCO以使内部反馈信号与外部基准时钟信号对准。 控制电路还锁定DCO的调制频率，并监视数字倍频电路的状态以保持锁定。

公开(公告)号：US20080266000A1

公开(公告)日：2008-10-30

申请号：US11740612

申请日：2007-04-26

申请人： Hung C. Ngo ,  Fadi H. Gebara ,  Jethro C. Law ,  Trong V. Luong

发明人： Hung C. Ngo ,  Fadi H. Gebara ,  Jethro C. Law ,  Trong V. Luong

IPC分类号： H03L7/08

CPC分类号： H03L7/093 ,  H03L7/0991 ,  H03L7/18

摘要： A digital frequency multiplier circuit is disclosed. The digital frequency multiplier circuit includes a digitally controlled oscillator (DCO), a phase detector and a control circuit. The DCO generates an internal feedback signal. The phase detector detects a phase difference between the internal feedback signal and an external reference clock signal. Coupled between the phase detector and the DCO, the control circuit adjusts the DCO to align the internal feedback signal with the external reference clock signal after a phase difference between the internal feedback signal and the external reference clock signal has been detected. The control circuit also locks a modulation frequency of the DCO and monitors the state of the digital frequency multiplier circuit in order to maintain the lock.

摘要翻译： 公开了一种数字倍频器电路。 数字倍频器电路包括数字控制振荡器（DCO），相位检测器和控制电路。 DCO产生内部反馈信号。 相位检测器检测内部反馈信号和外部参考时钟信号之间的相位差。 在相位检测器和DCO之间耦合，在内部反馈信号和外部参考时钟信号之间的相位差被检测到之后，控制电路调节DCO以使内部反馈信号与外部基准时钟信号对准。 控制电路还锁定DCO的调制频率，并监视数字倍频电路的状态以保持锁定。

公开(公告)号：US20080116938A1

公开(公告)日：2008-05-22

申请号：US11560440

申请日：2006-11-16

申请人： Hung C. Ngo ,  Peter Juergen Klim ,  Jente B. Kuang ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Mathews

发明人： Hung C. Ngo ,  Peter Juergen Klim ,  Jente B. Kuang ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Mathews

IPC分类号： H03K19/096

CPC分类号： H03K19/0963 ,  H03K19/0013

摘要： A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The dynamic node is coupled to an output with an inverting logic circuit. A hybrid keeper circuit, coupled to the dynamic node, uses a parallel NFET and a first PFET to produce the same current as a larger PFET when operated with a high voltage power supply. The common node of the combination is coupled to the dynamic node by second PFET larger than the first PFET in one embodiment. At high voltage, the hybrid keeper provides a strong keeper current when potential noise is highest. The hybrid keeper current is automatically reduced at low voltage allowing performance to be maintained while keeping the effective noise immunity of the high voltage operation.

摘要翻译： 动态逻辑门具有响应于时钟信号的预充电阶段和具有多个逻辑输入的逻辑树预充电的动态节点，用于在响应于时钟信号的时钟信号的估计阶段期间评估动态节点 逻辑输入的布尔组合。 动态节点与反相逻辑电路耦合到输出端。 耦合到动态节点的混合保持器电路使用并联NFET和第一PFET在用高压电源操作时产生与较大PFET相同的电流。 在一个实施例中，组合的公共节点通过大于第一PFET的第二PFET耦合到动态节点。 在高电压下，当潜在噪声最高时，混合式保持器提供强的保持电流。 混合保持器电流在低电压下自动降低，从而保持性能得以保持，同时保持高电压工作的有效抗噪声能力。

公开(公告)号：US07414436B1

公开(公告)日：2008-08-19

申请号：US11877898

申请日：2007-10-24

申请人： Peter J. Klim ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Mathews

发明人： Peter J. Klim ,  Jethro C. Law ,  Trong V. Luong ,  Abraham Mathews

IPC分类号： H03K19/00

CPC分类号： H03K19/0963

摘要： A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

摘要翻译： 具有有限开关动态逻辑门的电路，其具有前端逻辑电路和锁存器。 前端逻辑电路的输出连接到锁存器的输入，前端逻辑电路评估施加到前端逻辑电路的一组输入信号以产生输出信号。 锁存器接收并保持输出信号。 电路还具有逻辑电路，其输出端连接到前端逻辑电路中的时钟输入端。 逻辑电路响应于从时钟源接收时钟信号而产生修改的时钟信号，并且修改的时钟信号具有提供最小时间段的持续时间，用于前端逻辑以评估该组输入信号并产生 输出信号。