利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

31 条记录 (耗时 0.022 秒)

    Semiconductor memory delay circuit
    1.
    发明授权
    Semiconductor memory delay circuit 失效
    半导体存储延迟电路

    公开(公告)号：US06867628B2

    公开(公告)日：2005-03-15

    申请号：US10405357

    申请日：2003-04-03

    申请人： Ji-Ho Cho ,  Seung-Keun Lee

    发明人： Ji-Ho Cho ,  Seung-Keun Lee

    IPC分类号： G11C8/00 ,  G11C8/18 ,  H03K5/08 ,  H03K5/13 ,  H03K5/1534 ,  H03H11/26

    CPC分类号： G11C8/18 ,  H03K5/082 ,  H03K5/1534

    摘要： A circuit includes an input for receiving an input signal, a delay chain connected to the input for delaying the input signal, and a circuit configuration connected to the delay chain downstream of the input, the circuit configuration for supplying a voltage to the delay chain in response to the input signal.

    摘要翻译： 电路包括用于接收输入信号的输入端，连接到输入端的用于延迟输入信号的延迟链，以及连接到输入下游延迟链路的电路配置，用于向延迟链提供电压的电路配置 响应输入信号。

    Flash memory device having improved read operation speed
    2.
    发明授权
    Flash memory device having improved read operation speed 有权
    具有改善的读取操作速度的闪存设备

    公开(公告)号：US08553456B2

    公开(公告)日：2013-10-08

    申请号：US12768055

    申请日：2010-04-27

    申请人： Ji-Ho Cho

    发明人： Ji-Ho Cho

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C2211/5634

    摘要： Provided is a flash memory device. The flash memory device includes: a memory cell storing multi-bit data; a reference bias voltage supply circuit generating a reference bias voltage; an sense amplifier sensing the multi-bit data stored in the memory cell using the reference bias voltage; and a control circuit controlling the reference bias voltage supply circuit. The control circuit controls the reference bias voltage supply circuit to allow the reference bias voltage to be developed according to a change of a main word line voltage applied to the memory cell during a read operation.

    摘要翻译： 提供了一种闪存设备。 闪速存储器件包括：存储多位数据的存储单元; 产生参考偏置电压的参考偏置电压电路; 感测放大器，使用参考偏置电压感测存储在存储单元中的多位数据; 以及控制基准偏置电压供给电路的控制电路。 控制电路控制参考偏置电压供应电路，以允许根据在读取操作期间施加到存储器单元的主字线电压的变化来显影参考偏置电压。

    Decoders and decoding methods for nonvolatile memory devices using level shifting
    3.
    发明授权
    Decoders and decoding methods for nonvolatile memory devices using level shifting 有权
    使用电平转换的非易失性存储器件的解码器和解码方法

    公开(公告)号：US07724582B2

    公开(公告)日：2010-05-25

    申请号：US11933716

    申请日：2007-11-01

    申请人： Ji-Ho Cho

    发明人： Ji-Ho Cho

    IPC分类号： G11C16/06

    CPC分类号： G11C16/08 ,  G11C8/10

    摘要： A decoder for a nonvolatile memory device includes a level shifter configured to produce a first voltage at an output thereof responsive to a first state of a global word line and to produce a second voltage at the output responsive to a second state of the global word line. The decoder further includes a plurality of local word line drivers, each having an input coupled to the output of the level shifter, the respective local word line drivers configured to drive respective local word lines responsive to voltages on respective partial word lines when the output of the level shifter is at the first voltage and to drive the respective local word lines to a common voltage when the output of the level shifter is at the second voltage. The first state of the global word line may generate a third voltage at an input of the level shifter, the second state of the global word line may generate a fourth voltage at the input of the level shifter, and the first and second voltages may have opposite polarities.

    摘要翻译： 用于非易失性存储器件的解码器包括电平移位器，其被配置为响应于全局字线的第一状态在其输出处产生第一电压，并且响应于全局字线的第二状态在输出端产生第二电压 。 解码器还包括多个本地字线驱动器，每个本地字线驱动器具有耦合到电平移位器的输出的输入，各个本地字线驱动器被配置为响应于相应部分字线上的电压而驱动相应的本地字线，当输出 当电平移位器的输出处于第二电压时，电平移位器处于第一电压并且将各个本地字线驱动到公共电压。 全局字线的第一状态可以在电平移位器的输入处产生第三电压，全局字线的第二状态可以在电平移位器的输入处产生第四电压，并且第一和第二电压可以具有 相反的极性

    Voltage regulator for flash memory device
    4.
    发明授权
    Voltage regulator for flash memory device 有权
    闪存器件的稳压器

    公开(公告)号：US07512010B2

    公开(公告)日：2009-03-31

    申请号：US11760829

    申请日：2007-06-11

    申请人： Ji-Ho Cho ,  Hyeok Kang

    发明人： Ji-Ho Cho ,  Hyeok Kang

    IPC分类号： G11C16/06

    CPC分类号： G11C16/12 ,  G11C5/147 ,  G11C16/08

    摘要： Provided is a voltage regulator of a flash memory device. Embodiments of the invention provide a voltage regulator that is configured to regulate either an internal pumping voltage or an external high voltage. In embodiments of the invention, the voltage regulator includes two switches having different switching current characteristics: when regulating the internal pumping voltage, the voltage regulator is configured to activate a switch having a relatively high switching current to output the regulated voltage; but when regulating the high external voltage, the voltage regulator is configured to activate a switch having a relatively low switching current to output the regulated voltage during at least a set-up time. In an embodiment of the invention, the voltage regulator may be configured to activate both switches to regulate the high external voltage after the set-up time. In yet another embodiment of the invention, after the set-up time, the voltage regulator may be configured to deactivate the switch having the relatively low switching current and activate the switch having the relatively high switching current to regulate the high external voltage.

    摘要翻译： 提供了闪存装置的电压调节器。 本发明的实施例提供一种配置成调节内部泵浦电压或外部高电压的电压调节器。 在本发明的实施例中，电压调节器包括具有不同开关电流特性的两个开关：当调节内部泵浦电压时，电压调节器被配置为启动具有相对较高开关电流的开关以输出调节电压; 但是当调节高的外部电压时，电压调节器被配置为激活具有相对低的开关电流的开关，以在至少建立时间期间输出调节的电压。 在本发明的一个实施例中，电压调节器可以被配置为激活两个开关以在设置时间之后调节高的外部电压。 在本发明的另一个实施例中，在设置时间之后，电压调节器可以被配置为使具有相对低的开关电流的开关去激活，并激活具有相对高的开关电流的开关以调节高的外部电压。

    Burst read circuit in semiconductor memory device and burst data read method thereof
    5.
    发明申请
    Burst read circuit in semiconductor memory device and burst data read method thereof 失效
    半导体存储器件中的突发读取电路及其突发数据读取方法

    公开(公告)号：US20070189074A1

    公开(公告)日：2007-08-16

    申请号：US11591580

    申请日：2006-11-02

    申请人： Ji-Ho Cho

    发明人： Ji-Ho Cho

    IPC分类号： G11C16/06 ,  G11C14/00 ,  G11C11/34

    CPC分类号： G11C7/1027 ,  G11C7/1051 ,  G11C7/106

    摘要： A semiconductor memory device conducts a burst read operation that avoids interrupt loading on a system. The memory device includes a memory cell array, a sense amplifier, a latch circuit and a burst mode control unit. The sense amplifier is configured to sequentially sense and amplifies data stored in the memory cell array. The latch circuit is configured for latching sensed data of the sense amplifier group and outputting the sensed data in response to a DUMP signal. The burst mode control unit is configured for detecting the length of invalid data included in the sensed data from a burst start address and controlling a point in time of DUMP signal generation according to the detection result to sequentially output only valid data among the sensed data.

    摘要翻译： 半导体存储器件进行突发读取操作，避免系统上的中断加载。 存储器件包括存储单元阵列，读出放大器，锁存电路和突发模式控制单元。 感测放大器被配置为顺序地感测和放大存储在存储单元阵列中的数据。 锁存电路被配置为锁存读出放大器组的检测数据，并响应于DUMP信号输出感测数据。 突发模式控制单元被配置为从突发起始地址检测包括在感测数据中的无效数据的长度，并且根据检测结果控制DUMP信号生成的时间点，以便仅顺序地输出感测数据中的有效数据。

    Memory cell array and non-volatile memory device
    6.
    发明授权
    Memory cell array and non-volatile memory device 失效
    存储单元阵列和非易失性存储器件

    公开(公告)号：US08050094B2

    公开(公告)日：2011-11-01

    申请号：US12198186

    申请日：2008-08-26

    申请人： Ji-Ho Cho

    发明人： Ji-Ho Cho

    IPC分类号： G11C11/34

    CPC分类号： G11C5/025 ,  G11C16/26

    摘要： A memory cell array, divided into multiple row memory cell arrays, includes multiple memory banks and sense amplifiers. Each of the memory banks includes multiple logical sectors and at least two sub-memory banks of multiple sub-memory banks. The at least two sub-memory banks are included in different row memory cell arrays, and each of the sub-memory banks includes multiple physical sectors. The sense amplifiers are dedicated to the sub-memory banks, respectively.

    摘要翻译： 分为多行存储单元阵列的存储单元阵列包括多个存储体和读出放大器。 每个存储体包括多个逻辑扇区和多个子存储体的至少两个子存储器组。 至少两个子存储体包含在不同的行存储单元阵列中，并且每个子存储体包括多个物理扇区。 读出放大器分别专用于子存储体。

    Decoders and decoding methods for nonvolatile semiconductor memory devices
    7.
    发明授权
    Decoders and decoding methods for nonvolatile semiconductor memory devices 有权
    非易失性半导体存储器件的解码器和解码方法

    公开(公告)号：US07616487B2

    公开(公告)日：2009-11-10

    申请号：US11933702

    申请日：2007-11-01

    申请人： Ji-Ho Cho

    发明人： Ji-Ho Cho

    IPC分类号： G11C16/06

    CPC分类号： G11C16/08 ,  G11C16/12

    摘要： A decoder for a non-volatile semiconductor memory device includes a level shifter configured to generate a negative first voltage at an output thereof responsive to a first state of a global word line and to generate a second voltage more positive than the first voltage responsive to a second state of the global word line. The decoder further includes a local word line driver having an input coupled to the output of the level shifter and configured to apply a voltage on a partial word line to a local word line when the output of the level shifter is at the first voltage and to apply the first voltage to the local word line when the output of the level shifter is at the second voltage.

    摘要翻译： 用于非易失性半导体存储器件的解码器包括电平移位器，其被配置为响应于全局字线的第一状态而在其输出处产生负第一电压，并产生响应于第一电压而比第一电压更正的第二电压 全球字线的第二状态。 解码器还包括本地字线驱动器，其具有耦合到电平移位器的输出的输入，并且被配置为当电平转换器的输出处于第一电压时将部分字线上的电压施加到局部字线，并且 当电平转换器的输出处于第二电压时，将第一电压施加到本地字线。

    DECODERS AND DECODING METHODS FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICES
    9.
    发明申请
    DECODERS AND DECODING METHODS FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICES 有权
    非线性半导体存储器件的解码和解码方法

    公开(公告)号：US20080106941A1

    公开(公告)日：2008-05-08

    申请号：US11933702

    申请日：2007-11-01

    申请人： Ji-Ho Cho

    发明人： Ji-Ho Cho

    IPC分类号： G11C16/06

    CPC分类号： G11C16/08 ,  G11C16/12

    摘要： A decoder for a non-volatile semiconductor memory device includes a level shifter configured to generate a negative first voltage at an output thereof responsive to a first state of a global word line and to generate a second voltage more positive than the first voltage responsive to a second state of the global word line. The decoder further includes a local word line driver having an input coupled to the output of the level shifter and configured to apply a voltage on a partial word line to a local word line when the output of the level shifter is at the first voltage and to apply the first voltage to the local word line when the output of the level shifter is at the second voltage.

    摘要翻译： 用于非易失性半导体存储器件的解码器包括电平移位器，其被配置为响应于全局字线的第一状态而在其输出处产生负第一电压，并产生响应于第一电压而比第一电压更正的第二电压 全球字线的第二状态。 解码器还包括本地字线驱动器，其具有耦合到电平移位器的输出的输入，并且被配置为当电平转换器的输出处于第一电压时将部分字线上的电压施加到局部字线，并且 当电平转换器的输出处于第二电压时，将第一电压施加到本地字线。