公开(公告)号：US06628545B1

公开(公告)日：2003-09-30

申请号：US10306080

申请日：2002-11-26

申请人： Jiang Li ,  Yider Wu ,  Zhizheng Liu

发明人： Jiang Li ,  Yider Wu ,  Zhizheng Liu

IPC分类号： G11C1604

CPC分类号： G11C16/3404

摘要： A memory circuit employed in a memory device is disclosed. According to one embodiment, the memory circuit comprises a first memory cell and a second memory cell. The first memory cell has a drain terminal connected to a bit line, which is connected to a sensing circuit. The first memory cell also has a control gate connected to a word line. The second memory cell also has a drain terminal connected to the bit line. The second memory cell has its control gate coupled to ground. The memory circuit supplies a source voltage greater than a ground voltage to a source terminal of the first memory cell and to a source terminal of the second memory cell such that the gate-to-source voltage of the second memory cell is less than the threshold voltage of the second memory cell.

摘要翻译： 公开了一种在存储器件中使用的存储器电路。 根据一个实施例，存储器电路包括第一存储单元和第二存储单元。 第一存储单元具有连接到位线的漏极端子，该位线连接到感测电路。 第一存储单元还具有连接到字线的控制栅极。 第二存储单元还具有连接到位线的漏极端子。 第二存储单元的控制栅极接地。 存储器电路将大于接地电压的源极电压提供给第一存储单元的源极端子和第二存储器单元的源极端子，使得第二存储器单元的栅极 - 源极电压小于阈值 第二存储单元的电压。

公开(公告)号：US06797565B1

公开(公告)日：2004-09-28

申请号：US10244369

申请日：2002-09-16

申请人： Jean Yee-Mei Yang ,  Yider Wu ,  Zhizheng Liu

发明人： Jean Yee-Mei Yang ,  Yider Wu ,  Zhizheng Liu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： Methods are disclosed for fabricating dual bit SONOS flash memory cells, comprising forming polysilicon gate structures over an ONO layer, and doping source/drain regions of the substrate using the gate structures as an implant mask. Methods are also disclosed in which dielectric material is formed over and between the gate structures, and the wafer is planarized using an STI CMP process to remove dielectric material over the polysilicon gate structures.

摘要翻译： 公开了用于制造双位SONOS闪速存储器单元的方法，包括在ONO层上形成多晶硅栅极结构，以及使用栅极结构作为注入掩模来掺杂衬底的源极/漏极区域。 还公开了在栅极结构之上和栅极结构之间形成电介质材料的方法，并且使用STI CMP工艺对晶片进行平面化以去除多晶硅栅极结构上的电介质材料。

公开(公告)号：US06869844B1

公开(公告)日：2005-03-22

申请号：US10701780

申请日：2003-11-05

申请人： Zhizheng Liu ,  Yider Wu ,  Jean Yee-Mei Yang

发明人： Zhizheng Liu ,  Yider Wu ,  Jean Yee-Mei Yang

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/02 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/105 ,  H01L27/0248 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

摘要： A structure for protecting an NROM from induced charge damage during device fabrication is described. The structure provides a discharge path for charge accumulated on the polygate layer during fabrication while providing sufficient isolation to ensure normal circuit operation.

摘要翻译： 描述了在器件制造期间保护NROM免受感应电荷损伤的结构。 该结构提供了在制造期间积聚在多晶硅层上的电荷的放电路径，同时提供足够的隔离以确保正常的电路操作。

公开(公告)号：US06754106B1

公开(公告)日：2004-06-22

申请号：US10245146

申请日：2002-09-16

申请人： Yider Wu ,  Jean Yang ,  Jiang Li

发明人： Yider Wu ,  Jean Yang ,  Jiang Li

IPC分类号： G11C1606

CPC分类号： G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

摘要： A load circuit for compensating for source side loading effects in a non-volatile memory. Specifically, embodiments of the present invention describe a reference cell that is coupled to a plurality of load circuits. At least one of the plurality of load circuits, an mth load circuit, comprises a select transistor coupled to m resistors that are coupled in series. The mth load circuit matches a source side loading effect of a corresponding mth memory cell located m memory cells away from a source line node on a source line coupling source regions in memory cells of a row of memory cells.

摘要翻译： 用于补偿非易失性存储器中源侧负载效应的负载电路。 具体地，本发明的实施例描述了耦合到多个负载电路的参考单元。 多个负载电路中的至少一个负载电路包括耦合到串联耦合的m个电阻器的选择晶体管。 第m个负载电路将位于m个存储单元的相应的第m个存储器单元的源极负载效应与源极线上的源极线节点耦合，该源极线耦合存储器单元的行的存储器单元中的源极区域。

公开(公告)号：US06331954B1

公开(公告)日：2001-12-18

申请号：US09894777

申请日：2001-06-28

申请人： John J. Wang ,  Jiang Li ,  Yider Wu

发明人： John J. Wang ,  Jiang Li ,  Yider Wu

IPC分类号： G11C1634

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C29/24 ,  G11C2029/5002 ,  G11C2029/5006

摘要： For electrically determining the level of misalignment of floating gate structures closest to a gate stack bending point in an array of flash memory cells, a plurality of test flash memory cells are formed with each test flash memory cell having a respective floating gate structure designed to be disposed a respective displacement distance from a respective gate stack bending point. An erase operation is performed for each of the test flash memory cells by biasing the test flash memory cells with voltages from a plurality of voltage sources. Each of the test flash memory cells are then biased with test voltages from the plurality of voltage sources. A respective current meter then measures a respective amount of current flowing through each of the test flash memory cells when biased with the test voltages. The level of misalignment is determined depending on which of the test flash memory cells conducts a current level that is greater than a threshold current level when biased with the test voltages. The level of misalignment is approximately equal to a highest one of the respective displacement distance corresponding to one of the test flash memory cells that conducts a current level that is greater than the threshold current level.

摘要翻译： 为了电气地确定最靠近闪速存储器单元阵列中的栅堆叠弯曲点的浮栅结构的未对准电平，形成多个测试闪存单元，每个测试闪速存储单元具有相应的浮栅结构，其设计为 从相应的栅堆叠弯曲点设置相应的位移距离。 通过利用来自多个电压源的电压偏置测试闪存单元，对每个测试闪存单元执行擦除操作。 然后每个测试闪存单元被来自多个电压源的测试电压偏置。 然后，相应的电流表随着测试电压的偏差测量流过每个测试闪存单元的相应电流量。 根据测试闪速存储器单元中的哪一个导通当被测试电压偏置时大于阈值电流电平的电流电平来确定未对准电平。 未对准的电平近似等于对应于传导大于阈值电流电平的电流电平的测试闪存单元之一的相应位移距离中的最高一个。

公开(公告)号：US10297607B2

公开(公告)日：2019-05-21

申请号：US13615723

申请日：2012-09-14

申请人： Takao Akaogi ,  Yider Wu ,  Yi-Hsiu Chen

发明人： Takao Akaogi ,  Yider Wu ,  Yi-Hsiu Chen

IPC分类号： H01L27/11565 ,  H01L21/762 ,  H01L27/11568 ,  H01L21/8234

摘要： A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.

公开(公告)号：US08012825B2

公开(公告)日：2011-09-06

申请号：US12350298

申请日：2009-01-08

申请人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

发明人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.

摘要翻译： 在制造双注入NOR NOR闪存结构的方法中，执行磷离子注入工艺，使得在两个栅极结构之间的半导体衬底中形成P掺杂漏极区，以与高掺杂漏极（HDD ）区域和轻掺杂漏极（LDD）区域。 因此，解决了HDD区域和LDD区域之间的连接处的电连接，并且解决了存储器中的载流子迁移率，同时解决了LDD区域的短沟道效应和穿通问题。

公开(公告)号：US20100227447A1

公开(公告)日：2010-09-09

申请号：US12399124

申请日：2009-03-06

申请人： Hung-Wei Chen ,  Yider Wu

发明人： Hung-Wei Chen ,  Yider Wu

IPC分类号： H01L21/8234

CPC分类号： H01L27/11519 ,  H01L29/40114

摘要： A flash memory device manufacturing process includes the steps of providing a semiconductor substrate; forming two gate structures on the substrate; performing an ion implantation process to form two first source regions in the substrate at two lateral outer sides of the two gate structures; performing a further ion implantation process to form a first drain region in the substrate between the two gate structures; performing a pocket implantation process between the gate structures to form two doped regions in the substrate at two opposite sides of the first drain region; forming two facing L-shaped spacer walls between the two gate structures above the first drain region; performing an ion implantation process to form a second drain region beneath the first drain region, both of which having a steep junction profile compared to the first source regions; and forming a barrier plug above the first drain region.

摘要翻译： 闪存器件制造方法包括以下步骤：提供半导体衬底; 在基板上形成两个栅极结构; 执行离子注入工艺以在两个栅极结构的两个侧向外侧处在衬底中形成两个第一源极区域; 执行另外的离子注入工艺以在所述两个栅极结构之间的所述衬底中形成第一漏极区; 在所述栅极结构之间执行凹穴注入工艺，以在所述衬底中在所述第一漏极区的两个相对侧形成两个掺杂区域; 在所述第一漏极区域之上的所述两个栅极结构之间形成两个面对的L形间隔壁; 执行离子注入工艺以在所述第一漏极区域下方形成第二漏极区域，所述第二漏极区域与所述第一源极区域相比具有陡峭的接合轮廓; 以及在所述第一漏极区域上方形成阻挡塞。

公开(公告)号：US20100197108A1

公开(公告)日：2010-08-05

申请号：US12761460

申请日：2010-04-16

申请人： Yider Wu

发明人： Yider Wu

IPC分类号： H01L21/28 ,  H01L21/762

CPC分类号： H01L29/78 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.

摘要翻译： 非易失性半导体制造方法包括以下步骤：制造在半导体衬底中分隔元件形成区域的元件隔离/绝缘膜; 通过第一栅极绝缘膜在半导体衬底上堆叠浮置栅极; 堆叠形成在浮置栅极上的第二栅极绝缘膜，并且通过第二栅极绝缘膜堆叠形成在浮置栅极上的控制栅极以及与控制栅极的自对准源极和漏极扩散区域。 在通过在选择栅极区域中局部蚀刻场氧化物膜的同时堆叠浮栅的过程中，随后是形成在元件形成区域中的浮栅并选择栅极区域，然后进行化学机械抛光（CMP）工艺， 浮动门和选择门同时形成。 因此，当存储单元小型化时，本发明允许该过程简单并减少缺陷密度。

公开(公告)号：US20070026675A1

公开(公告)日：2007-02-01

申请号：US11193409

申请日：2005-08-01

申请人： Unsoon Kim ,  Angela Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

发明人： Unsoon Kim ,  Angela Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

IPC分类号： H01L21/302

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11531

摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.

摘要翻译： 提供了一种用于形成存储器件的方法。 在衬底上形成氮化物层。 蚀刻氮化物层和衬底以形成沟槽。 在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。 沟槽填充有氧化物材料。 从存储器件剥离氮化物层，在沟槽上方形成台面。