公开(公告)号：US20100082939A1

公开(公告)日：2010-04-01

申请号：US12242411

申请日：2008-09-30

申请人： Jike Chong ,  Mikhail Smelyanskiy ,  Ram Ramanujam ,  Victor Lee

发明人： Jike Chong ,  Mikhail Smelyanskiy ,  Ram Ramanujam ,  Victor Lee

IPC分类号： G06F15/00

CPC分类号： G06F17/10

摘要： Methods and apparatus for implementing Brownian Bridge algorithm on Single Instruction Multiple Data (SIMD) computing platforms are described. In one embodiment, a memory stores a plurality of data corresponding to an SIMD (Single Instruction, Multiple Data) instruction. A processor may include a plurality of SIMD lanes. Each of the plurality of the SIMD lanes may process one of the plurality of data stored in the memory in accordance with the SIMD instruction. Other embodiments are also described.

摘要翻译： 描述了单指令多数据（SIMD）计算平台实现布朗桥算法的方法和装置。 在一个实施例中，存储器存储对应于SIMD（单指令，多数据）指令的多个数据。 处理器可以包括多个SIMD通道。 多个SIMD通道中的每一个可以根据SIMD指令处理存储在存储器中的多个数据之一。 还描述了其它实施例。

公开(公告)号：US20070143759A1

公开(公告)日：2007-06-21

申请号：US11300809

申请日：2005-12-15

申请人： Aysel Ozgur ,  Gregory Buehrer ,  Anthony Nguyen ,  Daehyun Kim ,  Victor Lee ,  Mikhail Smelyanskiy ,  Yen-Kuang Chen

发明人： Aysel Ozgur ,  Gregory Buehrer ,  Anthony Nguyen ,  Daehyun Kim ,  Victor Lee ,  Mikhail Smelyanskiy ,  Yen-Kuang Chen

IPC分类号： G06F9/46

CPC分类号： G06F9/5066 ,  G06F9/5033

摘要： In one embodiment, the present invention includes a method for performing a first level task of an application in a first processor of a system and dynamically allocating a second level task of the application to one of the first processor and a second processor based on architectural feedback information. In this manner, improved scheduling and application performance can be achieved by better utilizing system resources. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在系统的第一处理器中执行应用的第一级任务的方法，并且基于架构反馈将应用的第二级任务动态地分配给第一处理器和第二处理器之一 信息。 以这种方式，可以通过更好地利用系统资源来实现改进的调度和应用性能。 描述和要求保护其他实施例。

公开(公告)号：US09870267B2

公开(公告)日：2018-01-16

申请号：US11386443

申请日：2006-03-22

申请人： Anthony Nguyen ,  Engin Ipek ,  Victor Lee ,  Daehyun Kim ,  Mikhail Smelyanskiy

发明人： Anthony Nguyen ,  Engin Ipek ,  Victor Lee ,  Daehyun Kim ,  Mikhail Smelyanskiy

IPC分类号： G06F9/50 ,  G06F15/80

CPC分类号： G06F9/5044 ,  G06F15/8053 ,  G06F2209/509

摘要： Methods and apparatus to provide virtualized vector processing are disclosed. In one embodiment, a processor includes a decode unit to decode a first instruction into a decoded first instruction and a second instruction into a decoded second instruction, and an execution unit to: execute the decoded first instruction to cause allocation of a first portion of one or more operations corresponding to a virtual vector request to a first processor core, and generation of a first signal corresponding to a second portion of the one or more operations to cause allocation of the second portion to a second processor core, and execute the decoded second instruction to cause a first computational result corresponding to the first portion of the one or more operations and a second computational result corresponding to the second portion of the one or more operations to be aggregated and stored to a memory location.

公开(公告)号：US20070226735A1

公开(公告)日：2007-09-27

申请号：US11386443

申请日：2006-03-22

申请人： Anthony Nguyen ,  Engin Ipek ,  Victor Lee ,  Daehyun Kim ,  Mikhail Smelyanskiy

发明人： Anthony Nguyen ,  Engin Ipek ,  Victor Lee ,  Daehyun Kim ,  Mikhail Smelyanskiy

IPC分类号： G06F9/455

CPC分类号： G06F9/5044 ,  G06F15/8053 ,  G06F2209/509

摘要： Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.

摘要翻译： 描述了提供虚拟化向量处理的方法和装置。 在一个实施例中，对应于虚拟向量请求的一个或多个操作被分发到一个或多个处理器核以供执行。

公开(公告)号：US20070027870A1

公开(公告)日：2007-02-01

申请号：US11195224

申请日：2005-08-01

申请人： Daehyun Kim ,  Victor Lee ,  Anthony Nguyen ,  Mikhail Smelyanskiy

发明人： Daehyun Kim ,  Victor Lee ,  Anthony Nguyen ,  Mikhail Smelyanskiy

IPC分类号： G06F17/30

CPC分类号： G06F9/52 ,  G06F12/0806 ,  G06F2209/5017

摘要： A technique to perform concurrent updates to a shared data structure. At least one embodiment of the invention concurrently stores copies of a data structure within a plurality of local caches, updates the local caches with a partial result of a computation distributed among a plurality of processing elements, and returns the partial results to combining logic in parallel, which combines the partial results into a final result.

摘要翻译： 对共享数据结构进行并发更新的技术。 本发明的至少一个实施例将多个本地高速缓存中的数据结构的副本同时存储，并且在多个处理元件之间以部分计算结果更新本地高速缓存，并且将部分结果并行地返回到组合逻辑 ，将部分结果组合成最终结果。

公开(公告)号：US20190057300A1

公开(公告)日：2019-02-21

申请号：US16160466

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC分类号： G06N3/04 ,  G06F3/06 ,  G06F12/0875

摘要： The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nth layer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)st layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)st layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.

公开(公告)号：US20190057036A1

公开(公告)日：2019-02-21

申请号：US16160270

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC分类号： G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06

摘要： The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

公开(公告)号：US20190026015A1

公开(公告)日：2019-01-24

申请号：US15657614

申请日：2017-07-24

申请人： Victor Lee

发明人： Victor Lee

IPC分类号： G06F3/0485 ,  G06F3/0488 ,  G11B27/036 ,  H04N5/765

摘要： Some embodiments of the invention provide a computer based method of editing video, allowing users to add multimedia objects such as sound effect, text, stickers, animation, and template to a specific point in a timeline of the video. In some embodiments, the timeline of the video is represented by a simple scroll bar with a control play button, which allows a user to drag the control play button to a specific point on the timeline. This enables a user to pinpoint a specific frame within a video to edit. In some embodiments, a multimedia panel allows a user to select specific multimedia objects to add to the frame, with further manipulation. A mechanism to store these multimedia objects associated with the selected frame is defined in this invention. In some embodiments, frames with multimedia objects added will have indicators shown on the scroll bar, allowing the user to fast forward to that frame and further edit the frame.

公开(公告)号：US08627639B2

公开(公告)日：2014-01-14

申请号：US12234221

申请日：2008-09-19

申请人： Syed Y. Ali ,  Amy C. Biesenthal ,  Rishi Khullar ,  Victor Lee ,  Sean McGonagle ,  Greg Pankow

发明人： Syed Y. Ali ,  Amy C. Biesenthal ,  Rishi Khullar ,  Victor Lee ,  Sean McGonagle ,  Greg Pankow

IPC分类号： B65B1/04

CPC分类号： B65B5/103 ,  B65B5/12

摘要： A method in a computer system of distributing pills into containers for use by a patient includes obtaining from a memory a fill pattern including a mapping of each of a first plurality of pills to one of a first plurality of containers such that at least two of the first plurality of pills are mapped to the same one of the first plurality of containers, obtaining from the memory an attribute of each of the first plurality of pills such that at least two of the first plurality of pills differ in at least the obtained attribute, and automatically sorting the first plurality of pills according to the attribute of each of the plurality of pills according to a predefined order to generate an ordered list corresponding to an order of depositing the first plurality of pills into the first plurality of containers.

摘要翻译： 计算机系统中将药丸分散到用于患者使用的容器中的方法包括从存储器获得填充图案，填充图案包括将第一多个丸剂中的每一个与第一多个容器中的至少两个的映射， 将第一多个药丸映射到第一组多个容器中的相同的一个，从存储器获得第一组多个药片中的每一个的属性，使得至少两个第一组药片至少在所获得的属性中不同， 并且根据预定义的顺序根据多个药丸中的每一个的属性自动分选第一批药丸，以产生与将第一批药丸沉积到第一多个容器中的顺序相对应的有序列表。

公开(公告)号：US07802981B2

公开(公告)日：2010-09-28

申请号：US11752953

申请日：2007-05-24

申请人： Zg Liu ,  Victor Lee

发明人： Zg Liu ,  Victor Lee

IPC分类号： B29C45/44

CPC分类号： B29C45/332 ,  B29C33/44 ,  B29C2045/334 ,  B29L2031/08

摘要： A device for extracting the mold core and a mold assembly using the same are disclosed. The extracting device comprises a first gear, a plurality of first racks and a plurality of transmission assemblies, wherein the transmission assemblies and the corresponding first racks are spaced apart along the periphery of the first gear such that each transmission assembly is located between the first gear and first racks. The rotating motion of the first gear is transformed into a reciprocating motion of each of the first racks from a first position to a second position.

摘要翻译： 公开了一种用于提取模芯的装置和使用其的模具组件。 提取装置包括第一齿轮，多个第一齿条和多个传动组件，其中传动组件和对应的第一齿条沿着第一齿轮的周边间隔开，使得每个传动组件位于第一齿轮 和第一架。 第一齿轮的旋转运动被转换成每个第一齿条从第一位置到第二位置的往复运动。