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9 条记录 (耗时 0.03 秒)

    Branch target buffer and method of use
    4.
    发明授权
    Branch target buffer and method of use 有权
    分支目标缓冲区和使用方法

    公开(公告)号：US07609582B2

    公开(公告)日：2009-10-27

    申请号：US12052762

    申请日：2008-03-21

    申请人： Gi Ho Park

    发明人： Gi Ho Park

    IPC分类号： G11C8/00

    CPC分类号： G06F9/3806 ,  G06F9/3844

    摘要： A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line gating value derived from branch history data related to the instruction. Additionally, a branch prediction unit and a processor incorporating the BTB are disclosed, along with methods for operating the BTB.

    摘要翻译： 公开了存储与分支指令相关的数据条目的转移目标缓冲器（BTB）。 BTB有条件地使得能够响应于与BTB中的字线相关联的字线选通电路来访问数据条目。 字线选通电路存储从与指令相关的分支历史数据导出的字线门控值。 此外，公开了分支预测单元和结合BTB的处理器以及用于操作BTB的方法。

    BRANCH TARGET BUFFER AND METHOD OF USE
    5.
    发明申请
    BRANCH TARGET BUFFER AND METHOD OF USE 有权
    分支目标缓冲区和使用方法

    公开(公告)号：US20080168263A1

    公开(公告)日：2008-07-10

    申请号：US12052762

    申请日：2008-03-21

    申请人： Gi Ho Park

    发明人： Gi Ho Park

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3806 ,  G06F9/3844

    摘要： A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line gating value derived from branch history data related to the instruction. Additionally, a branch prediction unit and a processor incorporating the BTB are disclosed, along with methods for operating the BTB.

    摘要翻译： 公开了存储与分支指令相关的数据条目的转移目标缓冲器（BTB）。 BTB有条件地使得能够响应于与BTB中的字线相关联的字线选通电路来访问数据条目。 字线选通电路存储从与指令相关的分支历史数据导出的字线门控值。 此外，公开了分支预测单元和结合BTB的处理器以及用于操作BTB的方法。

    Cache memory controller and method for replacing a cache block
    6.
    发明授权
    Cache memory controller and method for replacing a cache block 有权
    高速缓存存储器控制器和替换高速缓存块的方法

    公开(公告)号：US08930630B2

    公开(公告)日：2015-01-06

    申请号：US13376271

    申请日：2009-09-02

    申请人： Gi Ho Park

    发明人： Gi Ho Park

    IPC分类号： G06F12/12

    CPC分类号： G06F12/127 ,  G06F12/128

    摘要： The present disclosure relates to a cache memory controller for controlling a set-associative cache memory, in which two or more blocks are arranged in the same set, the cache memory controller including a content modification status monitoring unit for monitoring whether some of the blocks arranged in the same set of the cache memory have been modified in contents, and a cache block replacing unit for replacing a block, which has not been modified in contents, if some of the blocks arranged in the same set have been modified in contents.

    摘要翻译： 本公开涉及一种用于控制其中两个或多个块被布置在同一组中的集合关联高速缓存存储器的高速缓存存储器控制器，该高速缓存存储器控制器包括：内容修改状态监视单元，用于监视是否排列了一些块 在同一组高速缓冲存储器中已经修改了内容，以及高速缓存块替换单元，用于替换未内容中修改的块，如果在同一组中排列的某些块已被内容修改。

    Branch target buffer and method of use
    7.
    发明授权
    Branch target buffer and method of use 有权
    分支目标缓冲区和使用方法

    公开(公告)号：US07471574B2

    公开(公告)日：2008-12-30

    申请号：US11080986

    申请日：2005-03-16

    申请人： Gi Ho Park

    发明人： Gi Ho Park

    IPC分类号： G11C7/00

    CPC分类号： G06F9/3806 ,  G06F9/3844

    摘要： A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line gating value derived from branch history data related to the instruction. Additionally, a branch prediction unit and a processor incorporating the BTB are disclosed, along with methods for operating the BTB.

    摘要翻译： 公开了存储与分支指令相关的数据条目的转移目标缓冲器（BTB）。 BTB有条件地使得能够响应于与BTB中的字线相关联的字线选通电路来访问数据条目。 字线选通电路存储从与指令相关的分支历史数据导出的字线门控值。 此外，公开了分支预测单元和结合BTB的处理器以及用于操作BTB的方法。

    Branch target buffer and method of use
    8.
    发明申请
    Branch target buffer and method of use 有权

    公开(公告)号：US20060092712A1

    公开(公告)日：2006-05-04

    申请号：US11080986

    申请日：2005-03-16

    申请人： Gi Ho Park

    发明人： Gi Ho Park

    IPC分类号： G11C7/10

    CPC分类号： G06F9/3806 ,  G06F9/3844

    摘要： A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line gating value derived from branch history data related to the instruction. Additionally, a branch prediction unit and a processor incorporating the BTB are disclosed, along with methods for operating the BTB.

    CACHE MEMORY CONTROLLER AND METHOD FOR REPLACING A CACHE BLOCK
    9.
    发明申请
    CACHE MEMORY CONTROLLER AND METHOD FOR REPLACING A CACHE BLOCK 有权
    高速缓存存储器控制器和替换缓存块的方法

    公开(公告)号：US20120084515A1

    公开(公告)日：2012-04-05

    申请号：US13376271

    申请日：2009-09-02

    申请人： Gi Ho Park

    发明人： Gi Ho Park

    IPC分类号： G06F12/12

    CPC分类号： G06F12/127 ,  G06F12/128

    摘要： The present disclosure relates to a cache memory controller for controlling a set-associative cache memory, in which two or more blocks are arranged in the same set, the cache memory controller including a content modification status monitoring unit for monitoring whether some of the blocks arranged in the same set of the cache memory have been modified in contents, and a cache block replacing unit for replacing a block, which has not been modified in contents, if some of the blocks arranged in the same set have been modified in contents.

    摘要翻译： 本公开涉及一种用于控制其中两个或多个块被布置在同一组中的集合关联高速缓存存储器的高速缓存存储器控制器，该高速缓存存储器控制器包括：内容修改状态监视单元，用于监视是否排列了一些块 在同一组高速缓冲存储器中已经修改了内容，以及高速缓存块替换单元，用于替换未内容中修改的块，如果在同一组中排列的某些块已被内容修改。